The impact of device parameter variations on the frequency and performance of VLSI chips

Samaan, Stefanie

doi:10.1109/iccad.2004.1382598

Cited by 46 publications

(26 citation statements)

References 5 publications

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“…Thus, the gate-to-gate correlation is assumed to come from the joint impact of intra-and inter-chip variability only. We believe this is reasonable because (a) the data on spatial correlation is typically not available, (b) spatially correlated components are not numerically significant [11] and (c) it is possible to use an additive model to bound the impact of any remaining spatially-correlated intra-chip variability.…”

Section: Statistical Modeling and Optimizationmentioning

confidence: 99%

Application of fast SOCP based statistical sizing in the microprocessor design flow

Mani

Sharma²,

Orshansky

2006

Proceedings of the 16th ACM Great Lakes Symposium on VLSI

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In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interior-point solution method. The new solution method is capable of solving a robust linear program, that is mapped onto a second-order conic program, an order of magnitude faster than the previously explored formulation. Our sizing algorithm is unique in that it represents variability in circuit delay analytically by formulating a robust linear program. The algorithm allows efficient and superior area minimization under statistically formulated timing yield constraints. In this paper, we also report the first use of statistical gate sizing in an industrial microprocessor design flow as a postsynthesis optimization step. Statistical delay models were generated for a 90nm CMOS standard cell library used in the design of an industrial low-power 32bit x86 microprocessor and practical issues related to iterative convergence were explored. When compared to the deterministic sizing, the area savings are 26% for the microprocessor module. The runtime of the algorithm is very low compared to existing statistical sizing methods, achieving an almost 15X speed-up, and scales as O(N 1.5 ), where N is the circuit size.

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Section: Statistical Modeling and Optimizationmentioning

confidence: 99%

Application of fast SOCP based statistical sizing in the microprocessor design flow

Mani

Sharma²,

Orshansky

2006

Proceedings of the 16th ACM Great Lakes Symposium on VLSI

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“…The magnitude of intradie channel length variations has been estimated to increase from 35% of total variations in 130 nm to 60% in 70 nm CMOS process and variation in wire width, height, and thickness is also expected to increase from 25% to 35% [7]. In CMOS 65 nm process, the parameters that affect timing the most are device length, threshold voltage, device width, mobility, and oxide thickness [8]. For process variation sensitive circuits such as SRAM arrays and dynamic logic circuits, these process variations may result in functional failure and yield loss [7].…”

Section: Introductionmentioning

confidence: 99%

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

Yelamarthi

Chen

2010

VLSI Design

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The complexity of timing optimization of high-performance circuits has been increasing rapidly in proportion to the shrinking CMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a timing optimization algorithm for CMOS dynamic logic and a Path Oriented IN Time (POINT) optimization flow for mixedstatic-dynamic CMOS logic, where a design is partitioned into static and dynamic circuits. Implemented on a 64-b adder and International Symposium on Circuits and Systems (ISCAS) benchmark circuits, the POINT optimization algorithm has shown an average improvement in delay by 38% and delay uncertainty from process variations by 35% in comparison with a state-of-the-art commercial optimization tool.

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“…In addition to well known issues of concurrent programming, reliability and power management in CMPs [27], [10], there is a newly emerging and significant obstacle as we move toward future CMPs with a large number of cores: process variation [15], [26], [29], [12], [17]. In deep sub-micron design technology, it is becoming increasingly difficult to control critical transistor parameters such as gate-oxide thickness, channel length, and dopant concentrations.…”

Section: Introductionmentioning

confidence: 99%

“…Our work is different from these prior studies because most of them do not focus on performance. Specifically, [15], [26], [29], [12], [17] discuss the impact of process variation on chips. In comparison, [11] and [9] focus on profit and yield, respectively.…”

Section: Introductionmentioning

confidence: 99%

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Process variation aware thread mapping for Chip Multiprocessors

Narayanan

Kandemir

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiprocessors (CMPs) for example, it is possible that identically-designed processor cores on the chip have non-identical peak frequencies and power consumptions. To cope with such a design, each processor can be assumed to run at the frequency of the slowest processor, resulting in wasted computational capability. This paper considers an alternate approach and proposes an algorithm that intelligently maps (and remaps) computations onto available processors so that each processor runs at its peak frequency. In other words, by dynamically changing the thread-to-processor mapping at runtime, our approach allows each processor to maximize its performance, rather than simply using chip-wide lowest frequency amongst all cores and highest cache latency. Experimental evidence shows that, as compared to a process variation agnostic thread mapping strategy, our proposed scheme achieves as much as 29% improvement in overall execution latency, average improvement being 13% over the benchmarks tested. We also demonstrate in this paper that our savings are consistent across different processor counts, latency maps, and latency distributions.With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiprocessors (CMPs) for example, it is possible that identicallydesigned processor cores on the chip have non-identical peak frequencies and power consumptions. To cope with such a design, each processor can be assumed to run at the frequency of the slowest processor, resulting in wasted computational capability. This paper considers an alternate approach and proposes an algorithm that intelligently maps (and remaps) computations onto available processors so that each processor runs at its peak frequency. In other words, by dynamically changing the thread-to-processor mapping at runtime, our approach allows each processor to maximize its performance, rather than simply using chip-wide lowest frequency amongst all cores and highest cache latency. Experimental evidence shows that, as compared to a process variation agnostic thread mapping strategy, our proposed scheme achieves as much as 29% improvement in overall execution latency, average improvement being 13% over the benchmarks tested. We also demonstrate in this paper that our savings are consistent across different processor counts, latency maps, and latency distributions.

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The impact of device parameter variations on the frequency and performance of VLSI chips

Cited by 46 publications

References 5 publications

Application of fast SOCP based statistical sizing in the microprocessor design flow

Application of fast SOCP based statistical sizing in the microprocessor design flow

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

Process variation aware thread mapping for Chip Multiprocessors

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