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The Infrared Emission Microscopy (IREM) has been used in the semiconductor industry to locate hot carrier emission and thermal emission sites in CMOS ICs. In this paper, new applications to wafer-level backside Photon Emission Microscopy (PEM) and Flip-chip package analvsis will be presented.At the die level, Photon Emission Microscopy (PEM) is a Straightforward procedure ofbiasing the device and collecting photons. At wafer-level, this task becomes complicated because there are the various dice on the reticle field and the numerous reticle fields on the wafer, and it is difficult to tell which die is the DUT from the backside. A new method for die location is developed before wafer-level Backside PEM can be performed. In this method, the wafer is powered by reversed biased voltage to clamp the current appropriate to the device technology, and then PEM acquisition is started. The die with emission is the target.Real-time X-ray (RTX) inspection is a conventional way to locate anomalies in solder bumps in Flip-chip packages. This procedure has become routine. The drawback ofRTX is its high capital costs and its limit. For a company where the real-time X-ray system is not available, IREM could be an alternative for failure analysis in Flip-chip packages. This application had been reserved for RTX.

a high degree of structural integrity in the splat-cooled amorphous samples, i.e., a structure having the homogeneity of the liquid and consisting of continuous Te chains with In, Ga, and Ge attached to broken bonds. However, annealed samples show extrinsiclike conduction from 0 to ~ 130"C, and both Sand logp show decrease linearly with respect to the decrease of temperature T. The effect of heat treatment interpreted as a structural disordering, appears due to atomic segregation at local areas.

This paper describes a method to "non-destructively" inspect the bump side of an assembled flip-chip test die. The method is used in conjunction with a simple metal-connecting "modified daisy chain" die and makes use of the fact that polished silicon is transparent to infra-red (IR) light. The paper describes the technique, scope of detection and examples of failure mechanisms successfully identified. It includes an example of a shorting anomaly that was not detectable with the state of the art X-ray equipment, but was detected by an IR emission microscope. The anomalies, in many cases, have shown to be the cause of failure. Once this has been accomplished, then a reasonable deprocessing plan can be instituted to proceed with the failure analysis.

Packages with the Modified Daisy-chain (MDC) die have been used increasingly to accelerate reliability stress testing of IC packaging during package development, qualification, and evaluation and reliability monitor programs [1]. Utilizing this approach in essence eliminates chip circuit failure mechanisms. Unlike packages with active die, in packages with the MDC die, when short occurred between two daisy-chain pairs of I/Os, there are four possibilities that can attribute to each pin of the two daisy-chain pairs. That makes the isolation of short failure difficult. Time Domain Reflectometry (TDR) is a well-described technique to characterize package discontinuity (open or short failure). By using a bare package substrate and a reference device, an analyst can characterize the discontinuity and localize it: within the package, the die-package interconnects, or on the die [2]. Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields generated by current. The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects [3]. In this paper, a new methodology that combines Resistance Analysis, TDR Isolation and SSM Identification for electrical debugging short in packages with the MDC die will be presented. Case studies will also be discussed.