Electrical bitmapping and physical failure analysis were used to detect a small silicide break within a memory circuit which led to severe yield loss on our 0.20 p i CMOS process. A parallel, two-phase approach was used to optinzize the titanium silicide formation process and the silicon suYface preparation prior to titanium silicide. Several process and mask tooling modifications were implemented as a result of these efforts, which led to added robustness of the silicide process module and dramatic increases in wafer probe yield.

Bitmap and electrical microprobe techniques were employed to detect and isolate NMOS gate depletion within the SRAM cells of our O.2Otm Complementary Poly CMOS process. This gate depletion problem led to a 3X drop-off in device drive current and about a 300mV increase in threshold voltage. These shifts in device performance produced massive circuit failures within memory circuits and zero yield at wafer probe. Experiments were performed towards conclusively identifying and resolving this gate depletion failure mechanism. Several process modifications were implemented towards eliminating the NMOS gate depletion problem without compromising our margin against PMOS boron penetration. These process improvements led to dramatic increases in probe yield.