To realize next-generation highly realistic sensation broadcasting systems, the research and development of 8K ultrahigh-definition television (UHDTV) systems have been promoted. To realize 8K video cameras, 33Mpixel sensors [1-2] and a full-resolution camera system that uses three 33Mpixel sensors [3] have been reported. However, the weight of the camera with three sensors is over 40kg because the camera requires a large-format color-separation prism. To reduce the size of the camera, single-chip imaging is a promising approach, and a compact single-chip 8K camera that weighs only 2kg has already been developed using a color 33Mpixel CMOS image sensor [4]. However, a conventional single-chip camera has a lower image quality than a full-resolution camera because the total pixel count of the single-sensor camera is only one-third of that of the three-sensor camera, and pixel interpolation is required to configure a full-resolution image. In this paper, a 133Mpixel sensor that can be operated at 60fps to realize a full-resolution 8K single-chip camera is described. To achieve both high speed and suitable ADC resolution, 32-column multiplexing analog readout circuitry and 14b high-speed redundant successive approximation register (SAR) ADCs [5] are adopted. As a result, a full-size image with a data rate of 128.71Gb/s at 60fps has been captured. Figure 6.2.1 shows the sensor block diagram. The total pixel array size is 15488(H) × 8776(V) including optical black pixels. The pixel design is a 2.45μm two-way vertically shared pinned photodiode. The readout of the array is addressed one physical pixel row at a time with 15,488 readout columns split between the top and bottom of the pixel array. The column readout circuit consists of a source-follower bias current (VLN), a programmable-gain amplifier (PGA), and two sets of sample-and-hold capacitor banks (SHCaps) for even-and-odd-row ping-pong operation. Analog data stored in the SHCaps are read out in parallel by 484 SAR-ADCs. Each SAR-ADC serially multiplexes 32 columns, and the resulting converter data are written into the SRAM line memory. Two banks of SRAM memory are used to provide pipelining of the ADC and SRAM readout to reduce the row time. The SRAM readout is further divided into 16 parallel ports to reduce the data rate. Each readout port outputs 960 columns, with the exception of the 4 edge corner ports that output an additional 32 optical black columns. CML output drivers are used to output 7b-wide data to a 574.56MHz DDR, achieving an aggregate data rate of 128.71Gb/s. The sensor block diagram is completed with distributed PLLs, SPI communication, and on-chip timing control logic. Figure 6.2.2 shows a simplified block diagram of the signal readout path and timing control logic blocks. The PGA, SHCaps, CMR, and ADC are similar to those described in [5], which enables us to design a large-format sensor at 60fps that fits into a 1D stitching reticle. Front-end multiplexing of the columns is optimized for 32 columns per CMR and a 14b SAR-ADC with a conversion r...

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