No abstract

This paper presents the trap layer engineered body-tied FinFET device for MLC NAND Flash application. The device design parameters for high density NAND Flash memory have been considered, and the advantages of FinFET structure and high-k blocking dielectric in such device have been demonstrated. Based on the WN nano-dot memory device, the trap layer engineering using nitride layer has been performed, and the results show that the memory window is improved from 2.6 V to 7.8 V by utilizing engineered trap layer at 14 MV/cm F-N programming, and it is proposed as a possible MLC NAND device structure.

The room temperature-operation of a single-electron metal-oxide-semiconductor (MOS) memory with a defined quantum dot fabricated by sidewall patterning technique based on conventional VLSI technologies has been demonstrated without the aid of electron beam (EB) lithography for the first time. Sidewall patterning technique shows a good uniformity and controllability as well as high throughput. The fabricated memory devices show quantized threshold voltage shifts at room temperature. Timedependant measurement of drain current shows discrete electron injection to the quantum dot. In addition, fabricated devices have good subthreshold swing and retention characteristics.

For the purpose of controllable characteristics, silicon single-electron tunneling transistors with an electrically formed Coulomb island are proposed and fabricated on the basis of the sidewall process technique. The fabricated devices are based on a silicon-on-insulator ͑SOI͒ metal-oxidesemiconductor ͑MOS͒ field effect transistor with the depletion gate. The key fabrication technique consists of two sidewall process techniques. One is the patterning of a uniform SOI nanowire, and the other is the formation of n-doped polysilicon sidewall depletion gates. While the width of a Coulomb island is determined by the width of a SOI nanowire, its length is defined by the separation between two sidewall depletion gates which are formed by a conventional lithographic process combined with the second sidewall process. These sidewall techniques combine the conventional lithography and process technology, and guarantee the compatibility with complementary MOS process technology. Moreover, critical dimension depends not on the lithographical limit but on the controllability of chemical vapor deposition and reactive-ion etching. Very uniform weakly p-doped SOI nanowire defined by the sidewall technique effectively suppresses unintentional tunnel junctions formed by the fluctuation of the geometry or dopant in SOI nanowire, and the Coulomb island size dependence of the device characteristics confirms the good controllability. A voltage gain larger than one and the controllability of Coulomb oscillation peak position are also successfully demonstrated, which are essential conditions for the integration of a single-electron tunneling transistor circuit. Further miniaturization and optimization of the proposed device will make room temperature designable single-electron tunneling transistors possible in the foreseeable future.

We have developed a patterning technique to define ultrafine lines with high density and good uniformity using sidewall structures. Approximately 50 nm multiple lines, which have 70 nm as the narrowest space between the lines, are defined by the pattern multiplication technique. Linewidths are measured at several points on wafers and their uniformity is verified. These patterns have a good uniformity ͑deviation 2.26 -4.35 nm͒. Also, die-to-die uniformity is very good. The advantage of this technique is the easy control ͑using sidewall width control͒ of the line and space of patterns. This technique is free from the proximity effect because of the process using a sidewall hard mask. Thus, it is expected that the pattern multiplication technique can be applied to fabricate single electron devices, quantum devices, and other nanoscale devices.