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For future short- and mid-range industrial applications, optical free-space communication systems are expected to play a major role. When moderate transmission rates (100 Mbps range) are required, optical wireless communications present a viable and promising technology supplemental to conventional radio wireless systems. Advanced approaches based on diversity techniques and adaptive signal processing show potential to achieve both high spatial coverage and high bit rates of more than 100 Mbps. Visible light communication systems using white phosphorescent LEDs present equally an interesting application potential, combining illumination with data transfer. When high data volumes (100 Gbps range) need to be transmitted, tailored optical data links provide a solution of choice. Exemplarily, a scalable (24 - 140 Gbps) optical data link is presented, developed for future implementation in maskless lithography systems. The link comprises a high-speed data buffer with synchronizable architecture and scalable throughput (N × 24 Gbps), an optical free space transmission solution, and, finally, a 45 channel low-noise optical receiver chip based on BiCMOS 0.6 µm technology

Maskless lithography is one of the possible solutions to manage the escalating mask costs and demands for faster production cycles. One of the major issues with the maskless lithography technology however is the management and transfer of the enormous data volumes required to define the chip structures. Ensuring competitive and reliable operation requires dedicated preparation and buffering of the lithography data to be transmitted to the exposure unit. An optimized dedicated architecture and careful signal integrity design for proper functionality are needed due to the high data rates and the highly parallelized system operation. This paper presents the implementation aspects and the design of a high-speed transmission system solution for maskless lithography systems. The introduced solution treats a field programmable gate array (FPGA) based implementation for a latency-sensitive high speed lithography system