The paper addresses the through silicon via (TSV) filling using electrochemical deposition (ECD) of copper. The impact of seed layer nature on filling ratio and void formation will be discussed with respect to via diameter and via depth. Based on the Spherolyte Cu200 the electrolyte for the copper electrochemical deposition was modified for good filling behavior. Thermomechanical modeling and simulation was performed for reliability assessment

For the electrochemical filling of through silicon vias (TSVs) the geometry of these vias as well as their quantity on the wafer have a severe influence on the electrochemical process parameters, in particular on the current process time profile. So the electrochemical deposition (ECD) current was investigated in dependence of the filling progress, the height-to-depth aspect ratio, and the quantity of high aspect ratio vias on the wafer. The same applies to the number of plating steps at constant current, their length, and the total process time. Valuable insights for the design of via filing recipes could be deduce thereof