Bit interference effects in an ultra-thin body, double-gate, trapped-charge-storage type non-volatile memory cell are investigated through two-dimensional device simulations. Though such device is more scalable and has a larger current drive, it is found that the bit states on the two sides of the "common" body would interact with each other if the body is too thin. The remote charge effect, the remote punch-through effect, and the suppressed read-through capability are clarified to be the major killing factors. If there is a higher intrinsic-V t along the cell's channel beyond the active thin-body regions, part of the created memory window will be shadowed. Such interferences would become the worst as these cells are arranged in an array having the common-gate feature. Index terms: interference, remote punchthrough effect, remote bit effect, V t shadowing effect, second-bit effect, ultra-thin body, double-gate, non-volatile memory cell Introduction Non-volatile memory market has seen explosive growth over the past decade due to the wide spread applications in portable devices. In order to achieve competitive bit cost, NAND flash manufactured by advanced technology is still urgent. Scaling challenges in floating-gate (FG) type NAND and NOR flash cell have been widely reported [1-2]. Many novel cell structures have been suggested to improve flash memory cell's scalability and bit density [3][4][5]. Among them, FinFET-like cell draws much attention since its superior gate controllability dramatically suppresses the DIBL effect that is detrimental for the ultra-short-channel device. Meanwhile, higher read current and more stored charges are obtained due to its enlarged channel width. In addition, trapped-charge storage concept has been seriously considered since it is thought to be free from FG-like interference effect [6]. Interestingly, it is reported that in a double-SONOS cell, the gate bias and the bit state of the "opposite" channel would affect the conduction current of the sensed bit [5]. It implies that the interference effect may originate from a remote gate/bit resides on the opposite side of the "common" thin-body. The purpose of this paper is to study the bit interference effect in a cell having an ultra-thin body and a double-gate structure through device simulations.Simulation approaches A 2D device simulator, MEDICI [7], is used throughout the study. The simulation structure is as shown in Fig.1(b) that emulates an intrinsic thin-body cell ( Fig.1(a) [5]). The reasons to utilize such structure are explained in the figure. For the U-shape cell [4] ( Fig.2(a)), a simplified structure is used here (Fig.2(b)). The explored phenomena and the physical causes are unchanged in the modified structures, however, the simulation stability and efficiency are much better. Another factor that may affect the cell characteristics is the array architecture. From the device point of view, the double-gate cell could be operated in the common-gate mode (CGM) [4,8] in which those two gates should be coupled simultaneously...
