The origin of the electron memory trap in an oxide-nitride-oxide structure deposited on n-type Si is investigated by both capacitance-voltage and deep level transient spectroscopy (DLTS). Two electron traps are observed near 0.27 and 0.54eV, below the conduction band minimum of Si and are identified as the nitride bulk trap and the Si–SiO2 interfacial trap, respectively. The trap depth, viz., vertical distribution of the electron trap, in both nitride bulk and Si–SiO2 interface, are also estimated from the bias voltage dependent DLTS.
We have investigated lateral conduction mid-infrared photodetectors using the
photoionization of holes in the valence band of self-assembled Ge/Si quantum
dots. A mid-infrared photocurrent signal was observed in the photon energy
range of 140–400 meV resulting from an intersubband transition in the valence
band of self-assembled Ge quantum dots and subsequent lateral transport of
photoexcited carriers in the SiGe conduction channel. The peak responsivity was
134 mA W−1 at a photon energy
of 240 meV at T = 10 K. Furthermore, the band structure of the Ge QD system was estimated using electrical
and optical measurements.
As a three-dimensional topological insulator (TI), bismuth telluride (Bi2Te3) has two-dimensional electron gas on its surface where negative quantum capacitance (NQC) can exist at a specific biasing condition. In order to experimentally confirm NQC in a TI, a metal–insulator–semiconductor (MIS) capacitor (i.e., metal–Bi2Te3–SiO2–silicon) is fabricated. The capacitance–voltage measurement of the MIS capacitor at 300 K shows that as the depletion capacitance in silicon decreases, the total capacitance of the MIS capacitor, which consists of two capacitors connected in series (i.e., insulator capacitor and depletion capacitor), increases in the depletion region at a frequency of 50 kHz. The amplified capacitance indicates the existence of NQC on the surface of the TI, and it originates from the strongly correlated electron system. The NQC of the TI opens avenues for sub-60-mV/decade steep switching silicon devices.
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