Analysis of electronic memory traps in the oxide-nitride-oxide structure of a polysilicon-oxide-nitride-oxide-semiconductor flash memory

Seo, Yujeong; Kim, K. C.; Kim, T. G.; Sung, Yun Mo; Cho, H. Y.; Joo, Moon Sig; Pyi, Seung-Ho

doi:10.1063/1.2830000

Cited by 26 publications

(10 citation statements)

References 11 publications

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“…These defects act like traps and influence the electrical transport and phototransport in these structures. 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 For instance, the dark current is reduced as the carrier concentrations decrease due to the trapping. This effect is compensated in the case of the phototransport by the decrease of the recombination rate if either the electrons or holes are trapped.…”

Section: Introductionmentioning

confidence: 99%

“…23,24,25 Different methods were used to investigate these traps. The deep level transient spectroscopy (DLTS) method, 4,5,9,10,13,19,26 is the most used for the investigation of the deep traps. The method is based on the measurement of a transient junction capacitance and allows determining the energy of the trapping levels, as well as the concentration and capture cross-section of the trapping centers.…”

Section: Introductionmentioning

confidence: 99%

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Stress-induced traps in multilayered structures

Ciurea

Lazanu

Stavarache

et al. 2011

Journal of Applied Physics

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The trap parameters of defects in Si/CaF 2 multilayered structures were determined from the analysis of optical charging spectroscopy measurements. Two kinds of maxima were observed. Some of them were rather broad, corresponding to "normal" traps, while the others, very sharp, were attributed to stress-induced traps. A procedure of optimal linear smoothing the noisy experimental data has been developed and applied. This procedure is a Electronic mail: ciurea@infim.ro 2 based on finding the minimal value of the relative error with respect to the value of the smoothing window. In order to obtain a better accuracy for the description of the trapping-detrapping process, a Gaussian temperature dependence of the capture crosssections characterizing the stress-induced traps was introduced. Both the normal and the stress-induced traps have been characterized, including some previously considered as only noise features.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Stress-induced traps in multilayered structures

Ciurea

Lazanu

Stavarache

et al. 2011

Journal of Applied Physics

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“…In our previous study, we examined the C-V hysteresis curve for SiO 2 and Cr-SrTiO 3 capacitors fabricated on Si substrates. 3,14 As a result, we found that the memory windows are 0 V for both samples, indicating that there is no charging effect in bulk or interfacial regions of the SiO 2 and Cr-SrTiO 3 layer. Therefore, the memory effect is believed to result from the nitride bulk and their interfacial layer.…”

Section: Resultsmentioning

confidence: 89%

“…1,2 However, significant challenges for the preservation of device endurance and retention of SONOS cells programmed and erased by direct tunneling is still a critical issue because of the thin tunnel oxide (Լ2.5 nm) needed for the tunneling of substrate electrons or holes. 3,4 Therefore, we tried to apply a resistance switching mechanism, known for its fast switching speeds (i.e., below 100 ns), to the SONOS structure in order to improve the memory performance. Consequently, a novel NAND flash concept using gate injection for the P/E operations has been developed in order to reduce the gate oxide degradation.…”

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confidence: 99%

Investigation of vertically trapped charge locations in Cr-doped-SrTiO3-based charge trapping memory devices

Seo

Song

et al. 2012

Journal of Applied Physics

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In this paper, vertically trapped charge location is investigated to understand the carrier-transport dynamics in chromium-doped strontium titanate (Cr-SrTiO3 (STO))-based charge trapping memory devices using a transient analysis method. The vertical location of trapped charges is found to move from the Cr-SrTiO3/Si3N4 interface to the bulk region of Si3N4 with an increasing of the electric field, and, particularly, available trap sites are limited at the Cr-SrTiO3/Si3N4 interface by hole injection from the Si substrate into the Si3N4 layer at a high electric field (EOX > 7 MV/cm). In addition, some of these charges passing across the SiO2 (OX) layer generate many Si-SiO2 interface traps (Dit: 1.58 × 1012 cm−2 eV−1) that may degrade the device. However, the trapping efficiency can be improved by using sufficiently thick ( > 10 nm) bottom layers and by preventing direct hole tunneling and thereby, reducing the interface trap density.

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“…In addition, we extrapolated ΔV FB against the read delay time to predict the long-term retention of the annealed samples A and B, and the values observed at 3 × 10 8 s (ten years) were 0.4 and 1.6 V, respectively, at room temperature. This result implies that the data retention in the two samples would be more than ten years at room temperature [26]- [28] in a P/E condition (±8 V at 1 ms). However, the data-retention time of sample B was longer than that of sample A.…”

Section: Resultsmentioning

confidence: 97%

Negative-/Positive-Bias-Instability Analysis of the Memory Characteristics Improved by Hydrogen Postannealing in MANOS Capacitors

Kim

Seo

et al. 2010

IEEE Trans. Device Mater. Relib.

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We report the effect of hydrogen annealing on the gate-leakage-current and switching characteristics of metalalumina-nitride-oxide-silicon (MANOS) capacitors by analyzing their negative-/positive-bias instability (NBI/PBI). One sample, namely, A, is annealed with rapid thermal annealing (RTA), and the other sample, namely, B, is first annealed with RTA and then further annealed in a furnace, using a N 2 −H 2 (98% nitrogen and 2% hydrogen) gas mixture. In the NBI/PBI experiments, the flatband voltage shift ΔV FB is observed to be smaller, i.e., the gate-leakage-current density is reduced for sample B at gate voltages less than ±3 V, a domain where trap-assisted tunneling is dominant. However, ΔV FB increases rapidly for the same sample at gate voltages larger than ±6 V, a domain where the modified Fowler-Nordheim tunneling (MFNT) is dominant, which indicates faster program-and-erase characteristics. These results show that additional hydrogen annealing can improve both device reliability and switching characteristics of the MANOS-type memory by reducing interface traps between the silicon substrate and silicon oxide layers, as well as turn-on voltages for MFNT.Index Terms-Flash memory, metal-alumina-nitride-oxidesilicon (MANOS), negative-bias (NB) temperature instabilities (NBTIs), passivation effect, positive-bias (PB) temperature instabilities (PBTIs), postannealing.

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Analysis of electronic memory traps in the oxide-nitride-oxide structure of a polysilicon-oxide-nitride-oxide-semiconductor flash memory

Cited by 26 publications

References 11 publications

Stress-induced traps in multilayered structures

Stress-induced traps in multilayered structures

Investigation of vertically trapped charge locations in Cr-doped-SrTiO3-based charge trapping memory devices

Negative-/Positive-Bias-Instability Analysis of the Memory Characteristics Improved by Hydrogen Postannealing in MANOS Capacitors

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