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A fully depleted silicon-on-insulator (FD SOI) device having an ultrathin buried oxide (BOX) with a 45-nm fully silicided (FUSI) NiSi gate, and a hybrid SOI/bulk complementary metal oxide semiconductor (CMOS) integration process have been developed. The optimal threshold voltage (V th ) for low stand-by power (LSTP) applications in FUSI gate silicon on thin BOX (SOTB) MOSFETs was achieved while keeping a lightly doped channel. By using back-gate bias, we have demonstrated the optimization of device power and performance and a reduction in V th variation after device fabrication. We have also shown that the characteristics of the integrated hybrid bulk transistor are comparable to those of conventional bulk transistors.