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The high‐frequency performance of switched‐capacitor filters is bounded mainly by the finite gain bandwidth product of operational amplifiers. In this paper, the effects of finite gain bandwidth product of operational amplifiers on the performance of FIR (transversal) filters using such amplifiers as delay elements (canonical circuit) is analyzed. Next, a new low‐power consumption FIR switched‐capacitor circuit for high frequencies, which we call a parallel cyclic‐type circuit (PCTC), is proposed. The proposed circuit does not use operational amplifiers as delay elements. Instead, switches and capacitors are used for both the delaying and the weighting operations. We present a basic circuit using subblocks, a circuit with reduced number of capacitors, and a modified circuit having plural operational amplifiers for higher‐frequency use. We then show the design of a fourthorder FIR filter employing PCTC. Under the condition that sampling frequency is one‐half of unity gain frequency of operational amplifier, computer simulations of fourth‐order transversal switched‐capacitor filters with canonical circuit and that with parallel cyclic‐type circuit are performed and the experimental results of these circuits using discrete components are also given. Both demonstrate that the parallel cyclic‐type circuit has significantly better performance than the canonical circuit.