This paper describes design criteria for high-density lowpower static RAM cells with a four-transistor two-resistor configuration. The states of the cell latch are expressed by a dc stability factor introduced from transfer curves of the inverters in the cell. The criteria feature using only static conditions for read/write/retain operations. The designed cell considering mask-misatignment measured 22.8 X 27.6 Mm with 2.5~m layout rules. From the evahration of dynamic characteristics, it was shown that the 16K RAM using the cell had a sufficient operating margin.

No abstract

No abstract

The high‐frequency performance of switched‐capacitor filters is bounded mainly by the finite gain bandwidth product of operational amplifiers. In this paper, the effects of finite gain bandwidth product of operational amplifiers on the performance of FIR (transversal) filters using such amplifiers as delay elements (canonical circuit) is analyzed. Next, a new low‐power consumption FIR switched‐capacitor circuit for high frequencies, which we call a parallel cyclic‐type circuit (PCTC), is proposed. The proposed circuit does not use operational amplifiers as delay elements. Instead, switches and capacitors are used for both the delaying and the weighting operations. We present a basic circuit using subblocks, a circuit with reduced number of capacitors, and a modified circuit having plural operational amplifiers for higher‐frequency use. We then show the design of a fourthorder FIR filter employing PCTC. Under the condition that sampling frequency is one‐half of unity gain frequency of operational amplifier, computer simulations of fourth‐order transversal switched‐capacitor filters with canonical circuit and that with parallel cyclic‐type circuit are performed and the experimental results of these circuits using discrete components are also given. Both demonstrate that the parallel cyclic‐type circuit has significantly better performance than the canonical circuit.

FIR transversal filters have been proposed using a parallel cyclic‐type circuit configuration which alleviates the performance degradation at higher frequencies due to the finite gain‐bandwidth product of op amps in switched capacitor filters. A parallel cyclic‐type circuit realizes the delay and weighting of the input signal with switches and capacitors without op amps. It is also of low‐power consumption because it requires only one op amp for its adder. This paper describes a method to implement direct form I IIR filters using a parallel cyclic‐type circuit. The performance degradation caused by the finite gain bandwidth product of the op amp and by parasitic capacitances is analyzed, both for the canonical circuit with the delay element using op amps and for the parallel cyclic‐type circuit. Also, a parallel cyclic‐type circuit is proposed for high‐frequency operations containing multiple adders. This circuit incorporates a novel feedback scheme using the “Look Ahead” calculation method. Finally, through experiments, the performance improvement by the parallel cyclic‐type circuits over the canonical and biquad circuits is demonstrated.