SC FIR interpolation filters using parallel cyclic networks

Improved switched-capacitor interpolators with reduced sample-and-hold effects

“…Besides the distortion-free response, the proposed improved SC circuit also offers extra advantages over the previous circuits [2], [16], [17], [20] in terms of the capacitance spread and total capacitor area, required SC branches, clock phases, and speed of the OTA's, as demonstrated in Table I. It is significant to point out that the reduction in capacitance spread times) and capacitor area is mainly attributed by the special gain scaling times) imposed by the proposed novel sampling techniques for improved SC interpolation.…”

“…6(b) with the MF SC delay line and only one time-shared output accumulator. This noncanonic realization saves one ADB and output accumulators at the expense of narrowing the time slots for amplifier settling to 1/ , which is nevertheless still better than that in [2], [16], [17], [20]. The new configuration of one output accumulator with multiplexed accumulation branches reduces the total capacitor area due to capacitance group scaling in each polyphase filter.…”

“…Assuming 1/5 of the phase (or overall settling time to be allocated for slewing, while the remaining 4/5 for linear settling , for the worst-case estimation, the OTA must be capable to drive the equivalent total capacitive loading to a certain output voltage step during the slewing time interval , and also be exponentially settled within 0.1% accuracy during the slewing interval (the closed-loop time constant is approximately /7). Thus, the required tail bias current of the OTA can be simply estimated as (17) where and are the tail current required in slewing and linear settling time intervals, respectively, and can be given by Therefore, the expected static power of the OTA is given by the product of the supply voltage and the , i.e., . It is worth pointing out that a final optimum solution of the tail current normally needs to be investigated according to the required specifications in terms of gain, speed, power, dynamic range, and noise, as well as with a necessary safety margin for counting the process parasitics and variations.…”

“…Such approach has the advantage of employing well-known SC circuit architectures, but its response is distorted by the shaping effect at a lower input sampling rate, and for high-frequency applications it leads to higher power and larger silicon area consumption. Specialized multirate SC interpolators [2], [14]- [17] have also been developed based on polyphase structures that could take advantage of the sampling rate increase inherent in the interpolation process [19].…”

“…For finite-impulse response (FIR) transfer functions, direct-form (DF) polyphase [2], parallel-cyclic (PC) polyphase [17], and differentiator-based (DB) nonrecursive polyphase [16] SC interpolators have been proposed. The former DF and PC architectures are not practical for high-selectivity filtering due to the resulting large number of SC branches and clock phases, which degrade the circuit performance with increased sensitivity to both capacitance ratio mismatches and switch timing.…”