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Abstract-The breakdown mechanism in LDMOS devices with high resistive drift region sustaining high-voltage applications is analyzed and explained. Holes generated by the impact-ionization in the drift region are found to hinder the formation of the breakdown condition by increasing the potential underneath the gate-overlap region. This mechanism is modeled and implemented into the compact model HiSIM_HV for circuit simulation. Good agreement of simulated characteristics with 2D-device simulation results has been achieved.

Specific features of high-voltage MOSFETs and their modeling are summarized based on HiSIM-HV, which has been developed on the basis of HiSIM (Hiroshimauniversity STARC IGFET Model) for bulk MOSFETs A consistent potential description across MOSFET channel and high resistive drift region is the characteristic feature of the HiSIM models. The HiSIM-HV model covers symmetric and asymmetric device types up to several 100V switching capability with reproduction of accurate scaling properties of the devices. D-6-1 (Invited) pp. 730-731

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MOSFET capacitance values in high-voltage laterally diffused MOSFETs, including the channel impurity concentration, which tails off along the channel from the source side to the drain side, are investigated. This pertinent doping inhomogeneity of the intrinsic MOSFET channel induces an additional electrostatic contribution to the amount of internal charges. With an emphasis on the deviations from homogeneous impurity-profile settings, the additional contribution was formulated within the framework of compact MOSFET models based on the surfacepotential description. The developed capacitance-model enhancement requires a solution for the drain-side potentials at two uniform impurity concentrations, each of which corresponds to the source-side and the drain-side concentration of the impurity profile with gradient, respectively. The developed approach is found successful for all drain-source voltages, where the resulting high-voltage MOSFET-specific features are observed.