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The increase of test time of embedded DRAM (e-DRAM is one of the key issues of System-on-chip (SOC) device test. This paper proposes to put the repair analysis finction on chip as Built In Self Repair (BISR). BISR is performed at 1661MHz as at-speed of e-DRAM with using low cost automatic test equipment (ATE). The area of the BISR is approximately 1.7mm2 about 2% of conventional SOC devices. Using error storage table form contributes to realize small area penalty of repair analysis function. e-DRAM functional test time was reduced about 20% less than conventional method at wafer level testing. Moreovel; the results of e-DRAM test and repair analysis using BISR is almost coincident with conventional method.

This paper describes a high performance scalable massively parallel single-instruction multiple-data (SIMD) processor and power/area efficient real-time image processing. The SIMD processor combines 4-bit processing elements (PEs) with SRAM on a small area and thus enables at the same time a high performance of 191 GOPS, a high power efficiency of 310 GOPS/W, and a high area efficiency of 31.6 GOPS/mm . The applied pipeline architecture is optimized to reduce the number of controller overhead cycles so that the SIMD parallel processing unit can be utilized during up to 99% of the operating time of typical application programs. The processor can be also optimized for low cost, low power, and high performance multimedia system-on-a-chip (SoC) solutions. A combination of custom and automated implementation techniques enables scalability in the number of PEs. The processor has two operating modes, a normal frequency (NF) mode for higher power efficiency and a double frequency (DF) mode for higher performance. The combination of high area efficiency, high power efficiency, high performance, and the flexibility of the SIMD processor described in this paper expands the application of real-time image processing technology to a variety of electronic devices.Index Terms-Image processor, power efficiency, area efficiency, SIMD, scalable architecture, fine grained processing element.

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