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An Organic/inorganic hybrid solar cells are cheap alternatives to conventional silicon-based solar cells. The devices take the advantages of high optical absorption and carrier mobility of inorganic semiconductors, while maintaining the easy processing attributes of polymers or other soft materials. However, the conduction of holes has been a major technical barrier for the advance of such novel devices. In this study, we propose the use of silver nanowires (AgNWs) to improve the series resistance of the hybrid solar cells and further to realize solution-processed silicon-based photovoltaics. The hybrid silicon heterojunction solar cells are demonstrated based on the composite of conductive polymer PEDOT:PSS directly spun-cast on a micro-textured n-type crystalline silicon wafer, followed by the Meyer rod coating of AgNWs as the frontal metal contacts. The cross linked AgNWs offer high transparency and low sheet resistance, which can be easily fabricated using low-cost and non-toxic materials. Moreover, the industrial-standard microscale surface textures improve the antireflection and carrier collection without increasing much surface recombination. As a result, the device current density voltage characteristics reveals a high power conversion efficiency of 6.8% under a calibrated illumination intensity of 1000 W/m 2 of the AM1.5G solar spectrum, shedding light into the attainment of rapid solution processed silicon hybrid heterojunction solar cells.

In high-level synthesis, resource sharing may result in a circuit containing false loops that create great difficulty in timing validation during the design sign-off phase. It is hence desirable to avoid generating any false loops in a synthesized circuit. Previous work [Stok 1992;Huang et al. 1995] considered mainly data path sharing for false loop elimination. However, for a complete circuit with both data path and control path, false loops can be created due to control logic sharing. In this article, we present a novel approach to detect and eliminate the false loops caused by control logic sharing. An effective filter is devised to reduce the computational complexity of false loop detection, which is based on checking the level numbers that are propagated from data path operators to inputs and outputs of the control path. Only the input/output pairs of the control path identified by the filter are further investigated by traversing into the data path for false loop detection. A removal algorithm is then applied to eliminate the detected false loops, followed by logic minimization to further optimize the circuit. Experimental results show that for the nine example circuits we tested, the final designs after false loop removal and logic minimization give only slightly larger area than the original ones that contain false loops.

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