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Advancing in the nanometer regime, parametric variations has made yield a critical parameter to be included right in the beginning of the design process. Low power circuits have to be designed keeping in mind power consumption, minimum performance levels and yield and find the best compromise between all three. Statistical techniques, Monte Carlo Analysis, using log-normal model has been used to study the effect of parametric variations in leakage dominant 65 nm clock network design. Power supply (Vdd) and threshold voltage (Vth) scaling along with length and device sizing optimization is used to achieve best compromise among power consumption, delay and yield depending on the target application. General guidelines based on final application are given.

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Global and Environmental variations together are responsible for differences in timing from one die to another for an ASIC design. The tried and tested method of corners and margins is still the dominant method in ASIC industry to assure the timing characteristics of a design. However, the increasing margins limit the scaling of maximum achievable frequency for a given die size, especially because of minimum pulse width violation. The importance of clock tree pulse-width variations due to global N-to-P mismatch is increasing with decreasing pulse width. To continue scaling the clock frequency, we may need to make application specific margins and corners. In this work, we have estimated the impact of pulse width variations on standard cells in a clock library using industrial models and spice simulations. We found that by unbalancing the first stage of a cell with respect to rise and fall edge in a multiple supply voltage design, we could halve the pulse width variations with minimal effect on delay and slew.Index Terms-Clock tree pulse width, global N-to-P mismatch

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