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Nickel silicide (NiSi) can improve the RF performance of SiGe hetero bipolar transistors (HBT) compared to cobalt silicide (Heinemann et al 2016 IEDM Tech. Dig. 51-4). In this paper, the impact of different procedures to form NiSi on HBT and MOS devices of a 0.13 μm BiCMOS cobalt silicide technology is studied. The different NiSi formations are carried out by partly or fully Ni consumption (PC, FC) for low temperature furnace and low pressure anneals. Our investigations indicate, PC results in rough silicide surfaces and substrate interfaces, whereas FC leads to smooth surfaces and interfaces associated with lower resistivities. FC nickel silicidation at 300 °C and 450 °C exhibits an excessive NiSi growth on the STI edges of n doped source drain (N + SD) regions, reducing the breakdown voltage to substrate or p well. An enhanced NiSi growth is found for all investigated silicide schemes on narrow P + SD regions along polysilicon gates. The leakage current of these structures is caused by enlarged lateral silicidation towards the gates. The enhanced lateral NiSi growth could be suppressed by partly Ni silicidation with furnace anneals at 200 °C or 230 °C.

In this work we study different SiGe epitaxial processes for the base realization of a heterojunction bipolar transistor. In particular we investigate the poly SiGe layer of external base contact region. Silane (SiH4) and disilane (Si2H6) based precursors were used for a chemical vapour deposition (CVD) process of the Si/SiGe/Si layer stack. Sheet resistances of the poly SiGe layer as well as the boron doping and germanium distribution before and after different rapid thermal annealing steps were analyzed. We show that for equal doping profiles in the single crystalline region and minor differences in the thickness of the poly SiGe region the use of a disilane based precursor is beneficial for a reduced external base resistance. Sheet resistance measurements a decrease by more than 60% with respect to the standard silane based SiGe layer.

The world’s fastest SiGe HBT was presented by Heinemann et al. at IEDM 2016, which was achieved among other measures by NiSi application. The BiCMOS integration of such HBTs requires a careful NiSi adjustment with respect to MOSFET leakage currents. The goal of this paper is to find out a NiSi or NiPtSi process, which results in low RS to increase fmax without degradation of MOSFET leakage currents. An fmax rise is demonstrated by a reduction of NiSi or NiPtSi RS to 4 Ω. A further RS lowering to 1.6 Ω with a corresponding fmax increase was achieved by NiSi layers formed by two-step 300/450°C anneals, which generate elevated MOSFET leakage currents. They can be inhibited for NiSi formed by 200/450°C anneals at the expense of elevated RS. NiPtSi significantly suppresses silicide pipes to the MOSFET channel even for 300/450°C anneals and is a promising choice for upcoming BiCMOS technologies.