Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH ) in p-channel MOSFETs has enabled a simplified gate-first high-κ/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with T inv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.Introduction:

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Abstract-High Performance Work Systems (HPWSs) as a new way of organizing work in general and of production work in particular provide an environment, where selforganized learning processes are enabled and fostered. In an extensive research project in two major Austrian manufacturing companies we currently investigate the applicability and the effects of HPWS including issues of learning and knowledge management. In this contribution we present the results of the first phase of this project discussing early empirical findings of an exploratory nature.

We describe a post-release die separation process for 1 0 0 silicon wafers with polysilicon surface micromachines using a combination of diamond scribing and mechanical breaking. The theoretical basis of scribing is reviewed and the theoretical relationship between scribe force and median crack depth was experimentally verified. Also the relationship between the scribe angle and the median crack depth as well as the stress to fracture is described. Scribe speed and scribe wear were also investigated. The results from our experiments were used to develop a process that had yields above 80% for two types of electrostatic MEMS actuators.