Urban sound management is required in a variety of fields such as transportation, security, water conservancy and construction, among others. Given the diverse array of available noise sensors and the widespread opportunity to connect these sensors via mobile broadband Internet access, many researchers are eager to apply sound-sensor networks for urban sound management. Existing sensing networks typically consist of expensive information-sensing devices, the cost and maintenance of which limit their large-scale, ubiquitous deployment, thus narrowing their functional measurement range. Herein, an innovative, low-cost, sound-driven triboelectric nanogenerator (SDTENG)-based self-powered sensor is proposed, from which the SDTENG is primarily comprised of fluorinated ethylene propylene membranes, conductive fabrics, acrylic shells, and Kapton spacers. The SDTENG-based sensor has been integrated with a deep learning technique in the present study to construct an intelligent sound monitoring and identification system, which is capable of recognizing a suite of common road and traffic sounds with high classification accuracies of 99% in most cases. The novel SDTENG-based self-powered sensor combined with deep learning technique demonstrates a tremendous application potential in urban sound management, which will show the excellent application prospects in the field of ubiquitous sensor networks.

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Data integrity is a key metric of security for Internet of Things (IoT) which refers to accuracy and reliability of data during transmission, storage and retrieval. Cryptographic hash functions are common means used for data integrity verification. Newly announced SHA-3 is the next generation hash function standard to replace existing SHA-1 and SHA-2 standards for better security. However, its underlying Keccak algorithm is computation intensive and thus limits its deployment on IoT systems which are normally equipped with 32-bit resource constrained embedded processors. This paper proposes two efficient SHA-3 ASIPs based on an open 32-bit RISC-V embedded processor named Z-scale. The first operation-oriented ASIP (OASIP) focuses on accelerating time-consuming operations with instruction set extensions to improve resource efficiency. And next datapath-oriented ASIP (DASIP) targets exploiting advance data and instruction level parallelism with extended auxiliary registers and customized datapath to achieve high performance. Implementation results show that both proposed ASIPs can effectively accelerate SHA-3 algorithm with 14.6% and 26.9% code size reductions, 30% and 87% resource efficiency improvements, 71% and 262% better maximum throughputs as well as 40% and 288% better power efficiencies than reference design. This work makes SHA-3 algorithm integration practical for both low-cost and high-performance IoT systems.

With mobile and wireless devices becoming pervasive, low-cost hardwares of security functions are being desired. A compact hardware implementation of the SM3 hash algorithm is presented in this paper. A SRAM is used to do message expansion function instead of shift registers which are used in common hardware implementations, and the values of A∼H and V0∼V7 registers are updated in the serial shift way when they are initialized and updated. The computation units are saved as much as possible. Compared with traditional designs, the store resources for message expansion function can be shared with other modules to reduce the cost of a system. The Synopsys' DC synthesis results show that the area of the compact SM3 is approximate 8277 GEs while its throughput can be as high as 276 Mbps. If the SRAM is shared with other modules, only 6904 GEs are required to implement the SM3 hardware module in the system. The compact architecture can be accommodated to resource-constrained systems for its advantages of low-cost and low-power.