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The designs of resistive RAM (ReRAM) macros are limited by 1) a small sensing margin, limited read-, and slow read access time ( ) caused by a high cell-resistance and small cell-resistance-ratio (R-ratio) and 2) poor power integrity and increased energy waste attributable to a large SET dc-current ( ) resulting from the wide distribution of write (SET)-times ( ). This study proposes a swing-sample-and-couple (SSC) voltage-mode sense amplifier (VSA) to enable an approximately greater sensing margin for lower and a faster read speed across a wide range, compared with conventional VSAs. A 4T self-boost-write-termination (SBWT) scheme is proposed tocut off the of devices with a rapid . The SBWT scheme reduces 99 of the with an area penalty below 0.5%. A fabricated 512 row 28 nm 1 Mb ReRAM macro achieved 404 ns when 0.27 V and confirmed the cutoff by the SBWT.Index Terms-ReRAM, RRAM, sense amplifier, voltage-mode sense amplifier, write driver. 0018-9200

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