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By incorporating the basic Constant Current (CC) configuration with the buffered direct injection (BDI) structure, a new readout circuit called the constant current buffered direct injection (CCBDI) is proposed for the uncooled bolometer detector FPAs. Due to the use of BDI structure, the offset is decreased and the linearity range is increase. Thus linearity, dynamic range, and uniformity are improved. An experimental chip of 64x64 CCBDI FPA readout circuit has be designed and fabricated by using 0.5 pm double-poly double-metal n-well CMOS technology with the cell size of 50x50 pm2. The measured linearity is 94.36% whereas the measured uniformity is 81.3%. Both measurement and simulation results have verified the advantageous features of the proposed CCBDI readout circuit. It is believed that the new CCBDI structure has a great potential in the applications of large uncooled bolometer FPAs.

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This paper presents a 2.5-8Gb/s transceiver for PCI Express Gen3.0/2.0/1.0 applications. To overcome channel loss of high bit rate application, a linear equalizer (LEQ) and decision feedback equalizer (DFE) are used to eliminate ISI effect, compensate channel loss, and improve BER performance for 28inch FR4 channel. The 3-tap feed-forward equalizer (FFE) is used to improve signal quality in transmitter. The resolution of de-emphasis and pre-shoot is up to 1/63 and 1/15. It also performs 0.8UIpp eye opening for 8Gb/s operation. A 2 nd order clock and data recovery (CDR) employs digital finite state machine to track phase difference and frequency between clock and data. The CDR can cover 0 to -5000ppm frequency offset of SSC modulation and achieve jitter tolerance of up to 0.2UIpp at 8Gb/s with a BER=10 -10 when all specified jitter sources is included. The integrated transceiver operates from 2.5Gb/s to 8Gb/s and consumes 235mA at 8Gb/s current with 0.95V supply voltage. The test-chip is implemented by flip chip layout and fabricated in TSMC 40nm 0.9V/1.8V CMOS technology. The area of transceiver is 725um x 615um.