An investigation of an SiGe CMOS process fulfilling low-thermal-budget requirements was carried out. Three different undoped layers were grown successively by MBE: a 20 nm buffer layer, a 15 nm SiGe layer and a 15 nm cap layer. The Ge concentration of the SiGe layer was either uniform 20% or linearly graded 0-40% from the substrate to the surface. A 50 nm thick undoped Si layer was grown for the reference devices. Anodic oxide and LTO were used as gate dielectrics. The annealing was performed at relatively modest temperatures. The SiGe p-MOSFETs were compared to the Si reference devices. We report an enhancement of the hole mobility up to 70% for the SiGe p-MOSFETs.

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Silicon germanium pMOSFETs with channel lengths down to 0.4m have been fabricated on limited area silicon germanium virtual substrates. The devices have a 5nm thick Si0.3Ge0.7 active layer grown by MBE on top of relaxed Si0.7Ge0.3 virtual substrate. Virtual substrates were grown on top of 10μm square silicon pillars defined by etching trenches around their perimeter into the original silicon substrate. This limits the area of the growth zone, which in turn promotes the relaxation of the virtual substrate. Electrical measurements on 2μm long channel devices show that the maximum mobility in the strained SiGe devices is 211cm2V-1cm-1, compared to 104cm2V-1cm-1 for silicon reference devices. This increase in hole mobility increases the current drive of 0.4m devices measured at Vgt=-2V, Vds=-2.5V from 154μA/m to 192μA/μm.

Two names have been omitted from the original list of authors. The correct list should read: R M Sidek , U N Straube , A M Waite , A G R Evans , C Parry , P Phillips , T E Whall , E H C Parker , L S Riley§ and S Hall§ ECS Department, University of Southampton, Southampton SO17 1BJ, UK Department of Physics, University of Warwick, Coventry, CV4 7AL, UK §  Department of Electrical Engineering and Electronics, University of Liverpool, Brownlow Hill, L69 3GJ Liverpool, UK