In this brief, we present a simple close-form delay estimate, based on first and second order moments that handle arbitrary voltages and conductance effects for a lumped and distributed line. This proposed model introduces a simple tractable delay formula by incorporating conductance (G) into Resistance, Capacitance (RC) network by preserving the characteristics of the Elmore delay model. The RCG model attains quick steady state condition and the accuracy of the interconnect delay estimates can be improved by deploying the conductance effect. The simulation results shows the proposed interconnect scheme performance is better than the existing in terms of delay, power and the figure of merit. The performance analysis depicts that the proposed scheme has improved its figure of merit with minimum and maximum of 21.12% and 49.13%. The analysis is validated through extensive simulations on a 250 nm CMOS technology.

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The challenges of innovative IC technology typically come with various new design constraints in terms of circuit implementation, behaviour, scaling, and an accurate power-delay model to evaluate the circuit's performance. The circuit realization technique using GDI is gaining popularity because of its power and transistor utilization factors. Considering the core advantage of the GDI technique, this research presents the creation of new GDI library cells implemented using the MUX-based algorithm and its delay-power model. This research defines two goals; the former goal depicts the proposal of GDI library cells with full swing using a MUX-based signal connectivity model, and the later presents the mathematical delay-power model for the proposed GDI library cells. The number of attributes defined in the delay and power model incorporates minimum variables without sacrificing precision. It calculates the delay for simple RC networks and combinational circuits with multiple paths. The power model is given using the node activity factor and the power factor related to the internal node capacitances, wiring, and gate capacitances of the driving and receiving GDI nodes. The experimental results of this study, which conform to the specifications of the sub-micron library supported for the SilTerra 130 nm 6-metal layer fabricated for the CMOS n-well process, demonstrate that the proposed GDI library is indeed superior in terms of delay-transistor and power utilisation to PTL and CMOS technology. The simulation results reveal that there is 55 to 65 % improvement in terms of power and delay factor with the existing CMOS and PTL logic. The proposed delay model demonstrates that GDI cells require less logical effort than CMOS technology. The proposed power model shows that the node activity factor of the proposed GDI cells lies between 0.1 and 0.2, while in CMOS, it is between 0.1 and 0.3. Doi: 10.28991/ESJ-2023-07-04-022 Full Text: PDF

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