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This paper reports the design and the characterization of Single-Photon Avalanche Diodes (SPADs) fabricated in a standard 0.35 um CMOS technology aimed at very low noise and sharp timing response. We present the investigation on the breakdown voltage, photon detection efficiency (PDE), dark count rate (DCR) and timing response on devices with different dimensions and shapes of the active area. Results show uniform breakdown voltage among different structures, PDE above 50% at 420 nm, DCR below 50 cps at room temperature and timing response with no exponential tail and typical full-width at half-maximum of 77 ps and 120 ps for 10 um and 30 um active areas, respectively. The fabricated devices enable the fabrication of imagers with CMOS SPAD arrays suitable for advanced applications demanding extremely low noise and picosecond timing accuracy

In this work we present the structural and electrical characterization of sputter-deposited CoFe(B)/MgO/Si metal-insulator-semiconductor tunneling junctions for injection and detection of spin polarized current in silicon. The multilayers have been deposited in 700 nm deep trenches, patterned in thick SiO2 dielectric, on n- and p-doped wafers. The films inside the trenches are continuous with a correlated and low roughness. The MgO barrier grows amorphous without indication of pinholes. The dc and ac transport properties of the junctions were studied as a function of temperature and frequency. A relatively high interface trap density at the MgO/Si-interface is extracted from admittance spectra measurements. Transport is dominated by majority carriers in the case of n- doped and by minority carriers for the p-doped wafers. This leads to distinct rectification characteristics for the two wafer types, which would significantly influence the spin injection efficiency of the tunneling junctions