Wafer Level Package (WLP) volumes are steadily increasing due to their small package size and low manufacturing cost. However, applications to date have been mostly limited to die smaller than 5mm x 5mm. Solder joint fatigue due to stresses generated by the CTE mismatch between the die and the printed circuit board (PCB) limits adoption of WLP for large dies.Tessera's new compliant WLP technology greatly enhances thermal fatigue reliability of the package. A compliant layer under the solder joints effectively dissipates thermomechanical stress between the die and the PCB. FEA analysis was carried out to optimize compliant layer shape and mechanical properties, several materials were evaluated for this application, and prototype units were built. The prototype 9mm x 14mm packages exceeded 1600 cycles of temperature cycling from -40 o C to 125 o C. A compliant WLP package version with copper pins was also developed and tested for continuity at the wafer level. This structure has the potential to reduce wafer level test and burn-in (WLBT) costs substantially by eliminating the need for expensive die contact on the whole wafer contactor. IntroductionChip scale packages (CSPs) are widely used for electronic packages that require small form factor and high frequency performance. One example is a dynamic random access memory (DRAM). In the past, DRAMs were primarily packaged in small outline packages (TSOPs). However, the increased performance requirements of DDR2 DRAM could not be met with TSOPs. Consequently, CSPs have become the new standard.For many small die size components such as logic and analog ICs, WLP is a lower cost packaging solution than CSP due to elimination of packaging substrate, high parallelism in package processing and minimization of component handling. WLP also gives the smallest possible package form factor. However, the current reliable die size limit for a nonunderfilled WLP is about 5mm x 5mm. The limiting factor is thermal fatigue reliability. The coefficient of thermal expansion (CTE) for silicon is approximately 3 ppm/ o C while CTE for printed circuit board (PCB) is 14-18 ppm/ o C. As the package size increases, the stress generated by the large CTE mismatch between the die and the PCB causes the solder joint to crack and fracture. Some reliability improvement can be achieved by means of constraining the solder joint with a preapplied underfill 1 . However, the effect is limited and the approach increases cost. CSP packages face the same fundamental reliability challenge. The solution is the µBGA family of CSPs

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