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The main results concerning vacuum deposition of thin films to the silicon wafers and local electrochemical covering to the interconnecting frame have been described in the paper. These methods and technological conditions have been developed in order to meet the requirements of the process of VLSls packaging into plastic housings.

The creation of a multilevel system of interconnections in submicron integrated circuits makes it possible to reduce the electrical resistance of conductive tracks, parasitic capacitance between conductors, and increase the speed of microelectronic devices. It is proposed to form a transverse profile of the current-carrying tracks of a multilayer metallization system in the form of an isosceles trapezoid with angles at the lower base equal to 75–85 degrees. Etching of an aluminum-based alloy film is carried out in a plasma gas mixture of BCl3, Cl2, and N2 at the pressure of 150–250 mTorr and power density of 1.6–2.2 W/cm2, with the following component content, vol.%: BCl3 – 50–65; Cl2 – 25–35; N2 – the rest.

Destructive single event gate rupture (SEGR) occurring in the gate oxides of power MOSFETs under impact of heavy ions is studied and modeled. SEGR cross section of power MOSFET with 70 nm oxide thickness as function of gate voltage was measured for four types of heavy ions. A predictive formula for the SEGR cross section is derived and validated. This formula can be used as a predictive instrument for computation of survival probability in a given spectrum of heavy ions in space environments.

Passivation of the film conductive system of integrated circuits makes it more reliable by increasing the resistance to electromigration. The problem of manufacturing a passivating layer on the formed current-conducting system of an integrated circuit, obtained in a single technological cycle, including isotropic plasma-chemical etching of an aluminum alloy layer to a depth of 8–12 nm and isotropic plasma-chemical nitriding of the surface of the obtained current-carrying tracks until the aluminum nitride thickness from 10 to 50 nm, is considered. This task makes it possible to form a dielectric film based on silicon dioxide on a silicon substrate with active regions, etch contact windows to active elements of the substrate in the dielectric film, deposit a barrier layer 0.005–0.050 µm thick, and deposit an aluminum alloy film 0.5–2.0 um and much more.