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In this paper, we develop an ontology-based framework for energy management in buildings. We divide the functional architecture of a building energy management system into three interconnected modules that include building management system (BMS), benchmarking (BMK), and evaluation & control (ENC) modules. The BMS module is responsible for measuring several useful environmental parameters, as well as real-time energy consumption of the building. The BMK module provides the necessary information required to understand the context and cause of building energy efficiency or inefficiency, and also the information which can further differentiate normal and abnormal energy consumption in different scenarios. The ENC module evaluates all the information coming from BMS and BMK modules, the information is contextualized, and finally the cause of energy inefficiency/abnormality and mitigating control actions are determined. Methodology to design appropriate ontology and inference rules for various modules is also discussed. With the help of actual data obtained from three different rooms in a commercial building in Singapore, a case study is developed to demonstrate the application and advantages of the proposed framework. By mitigating the appropriate cause of abnormal inefficiency, we can achieve 5.7%, 11.8% and 8.7% energy savings in Room 1, Room 2, and Room 3 respectively, while creating minimum inconvenience for the users.

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Smart cameras are among the emerging new fields of electronics. The points of interest are in the application areas, software and IC development. In order to reduce cost, it is worthwhile to invest in a single architecture that can be scaled for the various application areas in performance (and resulting power consumption). In this paper, we show that the combination of an SIMD (single-instruction multiple-data) processor and a general-purpose DSP is very advantageous for the image processing tasks encountered in smart cameras. While the SIMD processor gives the very high performance necessary by exploiting the inherent data parallelism found in the pixel crunching part of the algorithms, the DSP offers a friendly approach to the more complex tasks. The paper continues to motivate that SIMD processors have very convenient scaling properties in silicon, making the complete, SIMD-DSP architecture suitable for different application areas without changing the software suite. Analysis of the changes in power consumption due to scaling shows that for typical image processing tasks, it is beneficial to scale the SIMD processor to use the maximum level of parallelism available in the algorithm if the IC supply voltage can be lowered. If silicon cost is of importance, the parallelism of the processor should be scaled to just reach the desired performance given the speed of the silicon.