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The design of Quantum Flux Parametron (QFP) majority logic circuits presents a number of unique constraints. For example, interconnects must be kept short and have a common small inductance. The former suggests that the bit-slice architecture is well suited to QFP circuits. In order to test this conjecture, a suitably complex logic circuit was designed and a small part of it was fabricated. A design for a 1Cfunction bitslice arithmetic-logic unit (ALU) was found that satisfied the constraints. It can compute on n-bit operands in 2n+4 QFP stages. A reduced version of the bit-slice ALU cell, containing 30 QFP's, was fabricated and successfully tested at low speed. The design experience showed that complex combinatorial QFP logic circuits are possible. Larger circuits will be feasible with computer-aided tools. I. INTRODUCITONThe Quantum Flux Parametron (QFP) [ 13 has been shown to operate at very high speeds [2]. Its application in logic devices, such as the majority gate [3], has also been demonstrated. Being a single flux quantum device, it also has a low power dissipation. These characteristics suggest that QFP logic circuits will be capable of high performance.The design of QIT logic circuits, however, presents a number of unique problems. Interconnects between QFP's must be kept short because of adverse effects on overall clock speed, circuit area and margin. In majority logic circuits, interconnect inductances, which make up most of the QFP load, are additionally required to be a fixed value. These two constraints and others cause much difficulty in the layout and routing design. On the logic design level, the short interconnect constraint restricts circuit architecture. Bit-slice architecture, besides using only short interconnects, should also be able to exploit the inherent pipelined nature of the QFP for high throughput.The feasibility of QFP majority gates for complex logic circuits is tested through schematic design of a bit-slice 16-function arithmetic-logic unit (ALU). This paper reports the results. The ALU was chosen because it was non-trivial, had a variety of gates, and was not too complex to be hand designed. Feasibility was further tested by fabrication and operation of a reduced version of the bit-slice cell. The 1-bit ALU, the largest logic circuit so far for a single flux quantum device, operated successfully at low speed.The rest of the paper is organized as follows. In section I1 the QFP majority logic gate family is reviewed, focusing on aspects affecting layout and routing design. In section I11 the reasons for restricting interconnect length are presented in Manuscript received Oct 17,1994. This work was supported by the Research Development Corportatim of Japan (JRDC). activation input QFp sign+ input LL load . inductor Fig. 1. The QFP circuit scheme. Shunt resistors shown are only needed if the junaions are hysteretic.detail. The method used to overcome problems in the design of fixed inductance interconnects is described. Logic design is presented in section IV. The experimental evalu...

Abstract-The Quantum Flux Parametron (QFP) is a SFQ-type logic device which uses a single flux quantum (SFQ) to represent 1-bit of information. QFP circuits use a multi-phase external ac power which also acts as the clock for synchronization, hence QFP circuits are highly pipelined. The clock frequency must be increased to improve the throughputs of the circuits, so the control of a high frequency clock is a key technology for the QFP. This paper describes a clock distribution technique which utilizes the characteristics of a standing wave. Using this technique, the operation of a 1-bit QFP shift register by a 4-phase clock up to 36 GHz is shown. In the 4-phase clock operation of QFPs, the input is given in phase 1, the QFP switches in phase 2, the output is held during phase 3, and the QFP resets in phase 4. Therefore, the 4-phase 36-GHz operation means that each QFP switches or resets in less than 7 ps.10 GHz must be achieved to enjoy the merits of a SFQ logic system.In order to show a high frequency clock distribution that is capable of exploiting potentials of the QFP, we have reported the operation of a 1-bit QFP shift register up to 16 GHz [ 101. Crosstalk with the clock signal is the major disturbance in the measurement. The aims of this paper are:(1) to show that this crosstalk can be reduced by actively using the characteristics of a standing wave which is a unique clock distribution scheme for QFP circuits, and (2) to demonstrate faster operation of the QFP shift register by using this scheme. The paper first presents a brief review of the QFP shift register. This is followed by the powering (clock distribution) system of QFP logic circuits. Finally, the high frequency operation of the QFP shift register is described. QFP SHET REGISTER