The anomalous diffusion of ion implanted boron into silicon is shown to be a transient effect with a decay time that decreases rapidly with increasing anneal temperature. The decay time is approximately 45 min at 800 °C and decreases to the order of a second at 1000 °C. The anomalous displacement in the low concentration region is greater at low temperatures but a larger fraction of the boron is redistributed at high temperature. Sheet resistance measurements agree with the idea that the moving fraction of the boron atoms is electrically active and limited to the intrinsic carrier concentration at the anneal temperature. The activation energy for the decay of the transient is greater than that for the diffusion coefficient, which makes an appropriate rapid thermal anneal cycle an important practical process in the fabrication of shallow p-n junctions.

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The effect of the implantation of silicon ions on the anomalous transient diffusion of ion-implanted boron is investigated. It is found that silicon ion fluences well below that necessary to amorphize the lattice substantially reduce the anomalous transient diffusion of subsequently implanted boron. The sheet resistance, however, is increased by the additional silicon implant. The implantation of silicon ions into activated boron layers causes additional anomalous diffusion at substantial distances beyond the range of the silicon ions. The anomalous motion is also reduced in regions where the damage is greater. The effects can be explained in terms of the generation of point defect clusters which dissolve during anneal and the sinking of point defects in the regions of high damage by the formation of interstitial type extended defects.

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In this paper a 0.25 pm SO1 CMOS technology is described. It uses imdepleted SO1 devices with nominal channel length of 0.15 pm, minimum channel length in the 0.1 pm range, supply voltage of 1 .S V, local interconnect, 6 levels of metal, artd same ground rules as the comparable bulk 0.25 pm CMOS. Key technology elements considered include device, penbrmance, reliability, ESD, and circuit functionality. Using this SO1 CMOS, a 4 Mb SRAM is demonstrated. This is the highest performance 0.25 pm CMOS technology reported to date. JNTRODUCTIONDespite many decades of work and promise of higher performance, SO1 CMOS technology has not been able to become the substra1.e for mainstream CMOS. The most important obstacle to SO1 becoming mainstream has been the floating-body ef'fects, and in particular the low nFET breakdown, which in turn severely limits high voltage screening of IC's. As; the CMOS technology moves into the 0.25 pm region, the supply voltage is reduced to 1.8 V.The breakdown of SO1 nFETs with LE^ in the 0.1 pm range is about 3 V. Lowered supply voltages, for the first time, have opened an opportunity for SO1 CMOS to become a mainstream technology. In developing the 0.25 pm SO1 CMOS technology, the goal has been to optimize the technology for maximum performance over the bulk, while keeping the standby current the same as a 0.25 bulk CMOS technology under the worst temperature condition and minimum channel length. In this work, the supply voltage chosen was based on achieving the highest possible performance. Devcloping a low power (voltage) technology was not part of this effort, although a 0.25 p m CMOS technology ht3s excellent low power potential.In addition to lhe usual technology issues addressed in a bulk CMOS, there are unique issues related to the floating-body effects (in particular pass gate leakage and history dependence of the delay) that should be addressed when developing an SO1 CMOS. These effects become more important as technology is applied to circuits which have tight timings or are sensitive to node leakage. In this work floating-body effects have been minimized to a great extent. The technology was applied to a 4 Mb SRAM, modified to work on SOI. Fast access time, as well as a wide operating voltage range is demonstrated. TECHNOLOGY and DEVICE RESULTSThis technology uses shallow trench isolation (!$TI), 40 A gate oxide, local interconnect, and the 6-lever1 A1 interconnect from 0.25 pm bulk CMOS [2-31. Figure 1 is an SEM of finished cross section (only the first 3 levels of BEOL shown for clarity). It has the same basic ground rules as a 0.25 pm technology. Only small density improvement over a 0.25 p m bulk technology is expected in a SO1 CMOS: Latch-up is of little concern in 0.25 pm 1.8V technologies, well contact in bulk technologies takes up little area, and most circuits are BEOL pitch limited. Use of STI eliminates any improvement that one might get in isolation in SOI. Non-depleted device was chosen for this technology [ 11. The effective channel length, LEFF, of this Figure 1-Cros...