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Copper wires were prepared in a silicon oxide matrix using the methods of semiconductor manufacturing and were electrically characterized. The width of the smallest structure was 40 nm and of the largest, 1000 nm; the heights were 50, 155, and 230 nm. Many samples of each size have been measured in order to perform a systematic investigation. The resistivity of the sample was extracted using the temperature coefficient of resistance. A significant increase in the resistivity was found for the small structures (roughly a factor 2 for 50-nm width). A model based on physical parameters was used in the analysis of the electrical data and very good agreement was obtained. The sensitivity of the various model parameters obtained by a best-fit procedure to the experimental data has been investigated. The impact of width and height on the resistivity, the influence of electron scattering at grain boundaries compared to surface scattering, and the impact of grain sizes and impurities will be discussed in detail.

We briefly review the status of the application of carbon nanotubes (CNTs) for future interconnects and present results concerning possible integration schemes. Growth of single nanotubes at lithographically defined locations (vias) has been achieved which is a prerequisite for the use of CNTs as future interconnects. For the 20 nm node a current density of 5·10 8 A/cm 2 and a resistance of 7.8 kΩ could be achieved for a single multi-walled CNT vertical interconnect.

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