Palladium diselenide (PdSe2), a peculiar noble metal dichalcogenide, has emerged as a new two-dimensional material with high predicted carrier mobility and a widely tunable band gap for device applications. The inherent in-plane anisotropy endowed by the pentagonal structure further renders PdSe2 promising for novel electronic, photonic, and thermoelectric applications. However, the direct synthesis of few-layer PdSe2 is still challenging and rarely reported. Here, we demonstrate that few-layer, single-crystal PdSe2 flakes can be synthesized at a relatively low growth temperature (300 °C) on sapphire substrates using low-pressure chemical vapor deposition (CVD). The well-defined rectangular domain shape and precisely determined layer number of the CVD-grown PdSe2 enable us to investigate their layer-dependent and in-plane anisotropic properties. The experimentally determined layer-dependent band gap shrinkage combined with first-principle calculations suggest that the interlayer interaction is weaker in few-layer PdSe2 in comparison with that in bulk crystals. Field-effect transistors based on the CVD-grown PdSe2 also show performances comparable to those based on exfoliated samples. The low-temperature synthesis method reported here provides a feasible approach to fabricate high-quality few-layer PdSe2 for device applications.

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The fabrication of trench-gate power MOSFETs with a SiGe channel region has been proposed to further improve the device performance. A larger Ge mole fraction of Si 1−x Ge x may cause a smaller on-state resistance but more degradation of the blocking voltage. A proper Ge mole fraction of 0.2 may be available, implementing a device with a blocking voltage of 30 V and a specific on-state resistance of about 0.70 cm. On the other hand, a gradually changed Ge mole fraction of the Si 1−x Ge x channel region may be employed to enhance the electric field in the channel region, and a specific on-state resistance of about 0.68 cm can be achieved. Moreover, for this device with a SiGe channel region, a thin n-SiGe layer may be used in the drain near the channel region. This scheme can even yield a specific on-state resistance of only about 0.66 cm which is 10% smaller than that caused by a conventional Si-channel device with the same process parameters.

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