This paper describes the VLSI design, layout, and testing of a Hybrid-SEED smart pixel array for a four-stage intelligent optical backplane. The Hybrid-SEED techinology uses CMOS silicon circuitry with GaAs-AIGaAs multiple-quantumwell modulators and detectors. The chip has been designed based on the Hyperplane architecture and is composed of four smart pixels which act as a logical 4-bit parallel optical channel. It has the ability to recognize a 4-bit address header, inject electrical data onto the backplane, retransmit optical data, and extract optical data from the backplane. In addition, the smart pixel array can accommodate for optical inversions and bit permutations by appropriate selections of multiplexers. Initial data pertaining to the electrical performance of the chip will be provided and a complete logical description will be given.

We describe a system demonstrator based on vertical-cavity surface-emitting lasers, metal-semiconductor-metal detectors, printed circuit board (PCB) level optoelectronic device packaging, a compact bulk optical relay, and novel barrel/PCB optomechanics. The entire system was constructed in a standard VME electrical backplane chassis and was capable of operating at >1.7 Gbit/s of aggregate data capacity. In addition to the component technologies developed, we describe operational testing and characterization of the demonstrator.

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