In order to evaluate the security of Application Specific Integrated Circuit (ASIC) implemented cryptographic algorithms at an early design stage, a Hamming distance model based power analysis is proposed. The Data Encryption Standard (DES) algorithm is taken as an example to illustrate the threats of differential power analysis (DPA) attack against the security of ASIC chip. A DPA attack against the ASIC implementation of a DES algorithm is realized based on hamming distance power model (HD model), and it realized the attack by successfully guessing the right 48-bit subkey. This result indicates that the power analysis attack based on the HD model is simple, rapid and effective for the design and evaluation of security chips.

In this paper, a SRAM array targeting IBM 130nm CMOS technology is proposed for ultra dynamic voltage scaling (UDVS) application with better immunity against process variation. A type of modified Schmitt Trigger inverter is adopted in the SRAM design, which guarantee stable operations in both superthreshold and subthreshold supply voltage regions. Testing results demonstrate that the proposed SRAM array functions well in the supply voltage range of 150 mV to 1200 mV. The optimum-energy supply voltage point is about 400 mV for proposed UDVS SRAM array. And the energy at 400 mV decreases by 62.5% compared to that at 1200 mV.

A low power 32-bit microcontroller using different kinds of low-power techniques to adapt to the dynamically changing performance demands and power consumption constraints of battery powered applications is designed and tested. Four power domains and six power modes are designed to fulfill low-power targets and meet different functional requirements. Varieties of low power methods such as dynamic voltage and frequency scaling (DVFS), multiple supply voltages (MSV), power gating (PG) and so on are applied. A novel zero steady-state current POR circuit which makes excellent performance in the chip’s OFF mode is also integrated. The SoC occupies 20 mm2 in a 0.18 um, 1.8 V nominal-supply, CMOS process. Test results show that the microcontroller works normally at the frequency of 70MHz and performs well in different power modes. Yet it only consumes 1.67μA leakage current in the OFF mode.

As semiconductor technology develops toward very deep submicron or even nanometer, power consumption per unit area increases dramatically. Scaling supply voltage into the subthreshold region provides significant energy reduction in logic circuits. However, low voltage and varies of environmental factors make it a challenge to design subthreshold circuit. This paper presents a method to modify standard cells to function well in subthreshold region. The main factors including process, voltage and temperature variables, noise and mismatch, which have more influence on the performance in the sub-threshold region than the strong inversion region. Typical static logics in the standard library TSMC65nm are analyzed by Monte Carlo analysis method when working in sub-threshold region, to find that logical failures occur to NAND VOL and NOR VOH before modified the sizes. After NAND's size increasing 85% and NOR's 370%, the failure has been eliminated and a good noise margin has been achieved.