The main purpose of this paper is to develop reliable and affordable tools and methodologies for the design, simulation, and fault analysis of controller area network (CAN) bus networks. In this paper, a behavioral model of a CAN bus transceiver is proposed and experimentally verified. Moreover, we developed a methodology to efficiently manage the trade-off concerning accuracy, simulation speed, and convergence issues which are usually involved in the simulation of large CAN bus networks. To this aim, three different architectures of the transceiver behavioral model have been implemented: They can be selected by the user to address specific requirements of intended analyses. The architectures are based on a set of behavioral models of the basic mixed-signal circuit building blocks of the transceiver. The models were implemented using the VHDL-AMS language. Signal integrity, fault analysis, power consumption analysis, corner analysis, etc., can be effectively and reliably implemented. Simulation and experimental results, which demonstrate our approach efficiency, are reported

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This paper presents a behavioral model of the non-linear on-resistance in S&H analog switches. The model is suitable for analysis and design of low-voltage sampled data systems. Simulated results using the ATMEL 0.24μm CMOS process are shown to validate the model. The Advanced-Compact-Mosfet model (ACM), a symmetric drain-to-source model, valid in the whole inversion level regime of MOS transistors, is used as reference

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