Layered materials of graphene and MoS2, for example, have recently emerged as an exciting material system for future electronics and optoelectronics. Vertical integration of layered materials can enable the design of novel electronic and photonic devices. Here, we report highly efficient photocurrent generation from vertical heterostructures of layered materials. We show that vertically stacked graphene–MoS2–graphene and graphene–MoS2–metal junctions can be created with a broad junction area for efficient photon harvesting. The weak electrostatic screening effect of graphene allows the integration of single or dual gates under and/or above the vertical heterostructure to tune the band slope and photocurrent generation. We demonstrate that the amplitude and polarity of the photocurrent in the gated vertical heterostructures can be readily modulated by the electric field of an external gate to achieve a maximum external quantum efficiency of 55% and internal quantum efficiency up to 85%. Our study establishes a method to control photocarrier generation, separation and transport processes using an external electric field.

The layered materials such as graphene have attracted considerable interest for future electronics. Here we report the vertical integration of multi-heterostructures of layered materials to enable high current density vertical field-effect transistors (VFETs). An n-channel VFET is created by sandwiching few-layer molybdenum disulfide (MoS2) as the semiconducting channel between a monolayer graphene and a metal thin film. The VFETs exhibit a room temperature on-off ratio >103, while at same time deliver a high current density up to 5,000 A/cm2, sufficient for high performance logic applications. This study offers a general strategy for the vertical integration of various layered materials to obtain both p- and n-channel transistors for complementary logic functions. A complementary inverter with larger than unit voltage gain is demonstrated by vertically stacking the layered materials of graphene, Bi2Sr2Co2O8 (p-channel), graphene, MoS2 (n-channel), and metal thin film in sequence. The ability to simultaneously achieve high on-off ratio, high current density, and logic integration in the vertically stacked multi-heterostructures can open up a new dimension for future electronics to enable three-dimensional integration.

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Bernal stacked (AB stacked) bilayer graphene is of significant interest for functional electronic and photonic devices due to the feasibility to continuously tune its band gap with a vertical electrical field. Mechanical exfoliation can be used to produce AB stacked bilayer graphene flakes but typically with the sizes limited to a few micrometers. Chemical vapor deposition (CVD) has been recently explored for the synthesis of bilayer graphene but usually with limited coverage and a mixture of AB and randomly stacked structures. Herein we report a rational approach to produce large-area high quality AB stacked bilayer graphene. We show that the self-limiting effect of graphene growth on Cu foil can be broken by using a high H2/CH4 ratio in a low pressure CVD process to enable the continued growth of bilayer graphene. A high temperature and low pressure nucleation step is found to be critical for the formation of bilayer graphene nuclei with high AB stacking ratio. A rational design of a two-step CVD process is developed for the growth of bilayer graphene with high AB stacking ratio (up to 90 %) and high coverage (up to 99 %). The electrical transport studies demonstrated that devices made of the as-grown bilayer graphene exhibit typical characteristics of AB stacked bilayer graphene with the highest carrier mobility exceeding 4,000 cm2/V·s at room temperature, comparable to that of the exfoliated bilayer graphene.