Vertically stacked multi-heterostructures of layered materials for logic transistors and complementary inverters

Abstract

The layered materials such as graphene have attracted considerable interest for future electronics. Here we report the vertical integration of multi-heterostructures of layered materials to enable high current density vertical field-effect transistors (VFETs). An n-channel VFET is created by sandwiching few-layer molybdenum disulfide (MoS2) as the semiconducting channel between a monolayer graphene and a metal thin film. The VFETs exhibit a room temperature on-off ratio >103, while at same time deliver a high current density up to 5,000 A/cm2, sufficient for high performance logic applications. This study offers a general strategy for the vertical integration of various layered materials to obtain both p- and n-channel transistors for complementary logic functions. A complementary inverter with larger than unit voltage gain is demonstrated by vertically stacking the layered materials of graphene, Bi2Sr2Co2O8 (p-channel), graphene, MoS2 (n-channel), and metal thin film in sequence. The ability to simultaneously achieve high on-off ratio, high current density, and logic integration in the vertically stacked multi-heterostructures can open up a new dimension for future electronics to enable three-dimensional integration.

Independent Band Modulation in 2D van der Waals Heterostructures via a Novel Device Architecture

“…Recently, considerable research interest has been intrigued by the vertically stacked vdWs integration of various 2DLMs, which provides infinite possibilities by overcoming the limitation of lattice matching and processing compatibility 6, 7, 8, 9, 10, 11, 12, 13, 14. Among various categories of vertically stacked vdWs heterostructured devices, the tunneling field effect transistor (TFET), which provides a promising sub‐60‐mV dec −1 subthreshold swing (SS), has been regarded as a promising application of vdWs heterostructure for future energy‐efficient electronics 15, 16, 17, 18, 19…”

High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits

“…15 CMOS is made from complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs), with matched threshold voltage and current level. CMOS logic circuits on two-dimensional (2D) materials have first been demonstrated on structures with two different layered materials, where one material is used for the n-type MOSFET (nMOS) device and a different material system is used for the p-type MOSFET (pMOS) 16,17 . Logic inverters have been fabricated with this heterogeneous combination, however these logic gates showed small gain (less than 2) and unmatched input output voltage, leading to zero noise margin 16,17 .…”

High Performance Amplifier Element Realization via MoS2/GaTe Heterostructures

“…Because the thickness of a 2DLM monolayer can be as thin as an atom and the surface is free of dangling bonds, 2DLMs surpass typical nanostructures that are plagued by dangling bonds and trap states. Neighboring 2DLM layers usually interact with each other by van der Waals force,14, 15 which allows for the integration of highly disparate materials with crystal lattice mismatching. There is considerable freedom in integrating 2DLMs and various nanoscale materials to create a set of diverse van der Waals heterostructures (vdWHs), with functions that could not be achieved previously.…”