SUMMARYThe multi-core technology can not only provide the computation in parallel but also avoid the redundancy costs by the communication and maintenance of multi-machine network structure. This paper uses the multi-core technology to achieve the parallelism of wavelet and wavelet packet transforms, so that the computation speed is increasing and the time is shortening in the practical applications. The parallel algorithms of wavelet and wavelet packet transforms, respectively, on the basis of POSIX thread and OpenMP are proposed and realized. The parallel results can meet the requirements by comparing parallel algorithms with the serial algorithms of single-layer and multi-layer transforms. For OpenMP, the paper takes the guidance statements to parallelize the loops of serial programs. In addition, the paper proposes one kind of nesting and non-nesting parallel means of wavelet packet transform and compares the parallel results with the serial programs. The experimental results show that the speedup is increasing with the amount of data and finally closing to 2. It is shown that the proposed parallel algorithms can improve the transform speed significantly. These parallel algorithms are applied in the harmonic analysis and data compression of power system, and a parallel strategy for compression with bitmap is proposed. The results show that the parallel algorithms of wavelet and wavelet packet transforms can improve the analysis and compression speed significantly.

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LDPC (Low Density Parity Check) is widely used in many telecommunication systems due to its excellent performance. However, real-time LDPC decoder in virtual radio system is difficult to realize. Taking CMMB (China Mobile Multimedia Broadcasting) for instance, this paper proposes a method to achieve high throughput decoder based on x86 processors which support SIMD (Single Instruction Multiple Data) instructions. By utilizing Normalized Min Sum decoding algorithm, normalized parameter as well as bit width of input variables and intermediate variables are determined. Then taking advantages of SIMD instructions, updating progress of variable nodes and check nodes in LDPC decoding algorithm is parallelized. Meanwhile, memory access operations are optimized as well. Tested on Intel Core i7-3960X, the throughput of the LDPC decoder using multithread processing can reach 92Mbps ∼ 722Mbps.

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