Detection and recognition of latent fingerprints play crucial roles in identification and security. However, the separation of sensor, memory, and processor in conventional ex-situ fingerprint recognition system seriously deteriorates the latency of decision-making and inevitably increases the overall computing power. In this work, a photoelectronic reservoir computing (RC) system, consisting of DUV photo-synapses and nonvolatile memristor array, is developed to detect and recognize the latent fingerprint with in-sensor and parallel in-memory computing. Through the Ga-rich design, we achieve amorphous GaOx (a-GaOx) photo-synapses with an enhanced persistent photoconductivity (PPC) effect. The PPC effect, which induces nonlinearly tunable conductivity, renders the a-GaOx photo-synapses an ideal deep ultraviolet (DUV) photoelectronic reservoir, thus mapping the complex input vector into a dimensionality-reduced output vector. Connecting the reservoirs and a memristor array, we further construct an in-sensor RC system for latent fingerprint identification. The system maintains over 90% recognition accuracy for latent fingerprint within 15% stochastic noise level via the proposed dual-feature strategy. This work provides a subversive prototype system of DUV in-sensor RC for highly efficient recognition of latent fingerprints.

Neuromorphic machines are intriguing for building energy-efficient intelligent systems, where spiking neurons are pivotal components. Recently, memristive neurons with promising bio-plausibility have been developed, but with limited reliability, bulky capacitors or additional reset circuits. Here, we propose an anti-ferroelectric field-effect transistor neuron based on the inherent polarization and depolarization of Hf0.2Zr0.8O2 anti-ferroelectric film to meet these challenges. The intrinsic accumulated polarization/spontaneous depolarization of Hf0.2Zr0.8O2 films implements the integration/leaky behavior of neurons, avoiding external capacitors and reset circuits. Moreover, the anti-ferroelectric neuron exhibits low energy consumption (37 fJ/spike), high endurance (>1012), high uniformity and high stability. We further construct a two-layer fully ferroelectric spiking neural networks that combines anti-ferroelectric neurons and ferroelectric synapses, achieving 96.8% recognition accuracy on the Modified National Institute of Standards and Technology dataset. This work opens the way to emulate neurons with anti-ferroelectric materials and provides a promising approach to building high-efficient neuromorphic hardware.

A self-organizing map (SOM) is a powerful unsupervised learning neural network for analyzing high-dimensional data in various applications. However, hardware implementation of SOM is challenging because of the complexity in calculating the similarities and determining neighborhoods. We experimentally demonstrated a memristor-based SOM based on Ta/TaOx/Pt 1T1R chips for the first time, which has advantages in computing speed, throughput, and energy efficiency compared with the CMOS digital counterpart, by utilizing the topological structure of the array and physical laws for computing without complicated circuits. We employed additional rows in the crossbar arrays and identified the best matching units by directly calculating the similarities between the input vectors and the weight matrix in the hardware. Using the memristor-based SOM, we demonstrated data clustering, image processing and solved the traveling salesman problem with much-improved energy efficiency and computing throughput. The physical implementation of SOM in memristor crossbar arrays extends the capability of memristor-based neuromorphic computing systems in machine learning and artificial intelligence.

Recent years have witnessed a surge of interest in learning representations of graph-structured data, with applications from social networks to drug discovery. However, graph neural networks, the machine learning models for handling graph-structured data, face significant challenges when running on conventional digital hardware, including the slowdown of Moore’s law due to transistor scaling limits and the von Neumann bottleneck incurred by physically separated memory and processing units, as well as a high training cost. Here we present a hardware–software co-design to address these challenges, by designing an echo state graph neural network based on random resistive memory arrays, which are built from low-cost, nanoscale and stackable resistors for efficient in-memory computing. This approach leverages the intrinsic stochasticity of dielectric breakdown in resistive switching to implement random projections in hardware for an echo state network that effectively minimizes the training complexity thanks to its fixed and random weights. The system demonstrates state-of-the-art performance on both graph classification using the MUTAG and COLLAB datasets and node classification using the CORA dataset, achieving 2.16×, 35.42× and 40.37× improvements in energy efficiency for a projected random resistive memory-based hybrid analogue–digital system over a state-of-the-art graphics processing unit and 99.35%, 99.99% and 91.40% reductions of backward pass complexity compared with conventional graph learning. The results point to a promising direction for next-generation artificial intelligence systems for graph learning.

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