A self-aligned triple patterning (SATP) process is proposed to extend 193nm immersion lithography to half-pitch 15nm patterning. SATP process combines lithography and spacer techniques in a different manner than the conventional selfaligned double patterning (SADP) by keeping the mandrel lines and the second spacers. Compared with other scaling candidates such as self-aligned quadruple patterning (SAQP), it can relax the overlay accuracy requirement of critical layers and reduce their process complexity by using less masks.A 3-mask SATP mandrel recession (SMR) technique is invented to relax the overlay requirement of critical layer patterning. We also successfully demonstrate a 2-mask SATP process concept for patterning critical layers that contain lines/spaces, pads and peripheral circuits, thus opening an opportunity to significantly reduce the process costs. If applied in deep nano-scale IC fabrication, SATP technique will have a fundamental impact on the design methodology of integrated circuits. Using both dry and immersion lithography, we have fabricated half-pitch 21nm and 15nm patterns with a SATP process. It is found that the mandrels (lines) co-defined by lithography and etch processes have worse line width roughness (LWR) than that of spacers, which poses a unique problem to CD control in IC design. As a major focus of our early-stage research, patterning small mandrels/lines in SATP process is a non-trivial challenge. Different materials have been screened and an optimal scheme of mandrel and spacer materials is necessary to meet key requirements (e.g., LER and CDU) of the lithographic performance.

Novel patterning approaches are explored to enable either more cost-effective manufacturing solutions or a potential paradigm shift in patterning technology. First, a simplified self-aligned quadruple patterning (SAQP) process is developed to extend 193nm immersion lithography to half-pitch 10nm patterning. A detailed comparison with other SAQP schemes is made, and we find the simplified SAQP process can significantly reduce process complexity and costs. On the other hand, the topographic effect on the spacer width causes difficulty in obtaining lines with equal CD, thus a CVD/etch solution must be searched to meet the CDU requirement.Moreover, a motion-induced frequency multiplication (MIFEM) concept is proposed; and specifically, we develop a stress-induced frequency multiplication (SIFEM) technique to produce half-pitch 9nm lines/spaces with no need of ebeam, imprint, or self-assembly technology. It allows us to apply standard semiconductor fabrication processes and equipment to drive down the half pitch of a spatially periodic pattern below 10nm. The resolution of this patterning technique is dependent on the CD of spacers and their gaps regardless of optical resolution of the lithographic tool. The final space CD is mainly related with the material property of the fluid used in SIFEM process. The main issues of SIFEM process include: adjusting the fluid property to tune the gap CD, designing the anchor structures and line route to control the strength and direction of film stress, and overlay methodology development, etc.Keywords: self-aligned quadruple patterning (SAQP), stress-induced frequency multiplication (SIFEM) SIMPLIFIED SELF-ALIGNED QUADRUPLE PATTERNINGSpacer self-aligned double patterning (SADP, [1]) combined with 193nm immersion lithography (single-exposure resolution at about 38nm) can drive the half pitch down to about 19nm. A straight forward method to further double the spatial frequency (i.e., about 10nm half pitch) is the self-aligned quadruple patterning (SAQP) technique [2].Two examples of the SAQP process to enable line/space density quadrupling are shown in Fig. 1. In both schemes, top APF mandrel/core (Advanced Patterning Film, a hard mask material developed by Applied Materials, Inc.) is patterned first. After that, nitride spacer is formed and APF core is stripped by an oxygen plasma etch. The main difference between scheme 1 and 2 is: nitride spacer in scheme 1 is transferred to the bottom APF which becomes the core of the second spacer (nitride); while in scheme 2, the second spacer (poly Si) is directly formed on nitride spacer. Apparently, the bottom APF core in scheme 1 has a symmetric shape which helps to form more uniform spacer structures. Direct spacer-on-spacer scheme 2 suffers from the more difficult CD control of final structures due to the asymmetric profile of the nitride spacer. In scheme 1, the bottom APF core is then stripped (in scheme 2, nitride is removed by phosphoric acid which does not attack poly Si and oxide), leaving the second spacers and resulting in spati...

No abstract

No abstract

The Sidewall Spacer Double Patterning (SSDP) technique, also referred to as Self-Aligned Double Patterning (SADP), has been adopted as the primary double patterning solution for 32nm technology nodes and below for flash memory manufacturing. Many are now looking to migrate the technique to DRAM and random Logic layers. However, DRAM and especially Logic have far more complex layout requirements than NAND-FLASH, requiring a more sophisticated use of the SSDP technique. To handle the additional complexities an automated electronic design tool was used to calculate optimal layout splits of a design target into 2 or 3 masks. The model was programmed with immersion lithography and dry-193nm lithography MRC input rules and on wafer performance was tested. We discuss the patterning needs from the trim-mask and the pad-mask and associated lithography process window requirements and alignment accuracies necessary to pursue 32nm and 22nm half-pitch designs.