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The use of energy balance and simplified hydrodynamic models for simulating GaAs devices is investigated. The simplified hydrodynamic model predicts velocity spikes that are not present in more detailed Monte Carlo simulation results. These velocity spikes are associated with overestimation of thermal diffusion. The simplified hydrodynamic model can predict terminal currents that are significantly lower than those predicted by the energy balance model. The differences between the models are significantly greater than those observed previously for silicon devices. The main conclusion of this study is that the energy balance model is preferable to the simplified hydrodynamic model as the basis for GaAs device simulation, but the energy balance model still needs refinement to improve the agreement with more general simulation and experimental results.

Self‐consistent electrothermal simulation of modern semiconductor devices is required for the accurate and efficient design and optimization of many semiconductor devices. The need to perform this type analysis in order to predict the behavior of power devices was realized many years ago. It is now clear that nonisothermal analysis can be very important for VLSI devices as well.

Stressors have been used since 90 nm technology to improve device performance to overcome the limitations of scaling. The stressors, including, -CPEN, TPEN, SMT, and e-SiGe to improve NMOS and PMOS drive current exhibit proximity dependence. In addition, unintentional stressors such as STI edge proximity introduce additional layout dependencies. Two devices with the same L and W can have significantly different drive strength depending on their surroundings. There have been limited studies to optimize the design layout to reduce the layout-dependent stress degradation. Circuit and layout designers have few tools they can use to quickly and effectively optimize the layout to reduce device degradation due to layoutdependent stress effects. In this paper, we present a comprehensive set of CAD utilities, and stress-related layout guidelines to optimize the layout for full custom macros to reduce the layout-dependent stress effects prior to doing full timing characterization, including stress effects.