No abstract

Long write times have been an industry wide concern regarding rising mask costs. The purpose of this study is to develop a simple model that can predict mask write time precisely, without an e-beam writer. With a good understanding of the trade-offs between design complexity and write time, mask makers can work with mask designers more closely to simplify design and minimize mask cost. This work compared several basic models including calculations based on write area with a fixed e-beam shot size, a software estimation with a pre-set exposure, and a mask stage settling time. Our proposed model uses a completely different approach to examine the correlation between layout complexity (vertices count, total line edge, figure, etc.) through a CATS layout segmentation and actual write time. It is found that write time is a strong function of layout figure, vertex count and total line edge. Errors between actual write time and estimated write time from the new model reduced from 7% on average on the current production software to 3%. Additionally, the new model can operate independent of the writer type and without fractured data being transferred onto a writer. Also provided are a few case studies to evaluate the interaction between write time and basic shape/OPC (optical proximity correction). Using a simple design shape and a better data snapping strategy can reduce write time up to 10 fold for applications in nano-imprint template manufacturing. Several strategies to reduce mask cost are proposed.

Self‐consistent electrothermal simulation of modern semiconductor devices is required for the accurate and efficient design and optimization of many semiconductor devices. The need to perform this type analysis in order to predict the behavior of power devices was realized many years ago. It is now clear that nonisothermal analysis can be very important for VLSI devices as well.

Recently, interest in the use of scanning probe microscopes (SPM) for metrology applications has grown. SPM can provide detailed topographical maps of reticles and wafers from which much useful data can be extracted. For example, CD measurements very near the bottom of sidewalls can be determined. Sidewall angles can be measured non-destructively. Micro-trenching (micro-loading) in etched quartz features on APSM can be characterized, and quartz bumps can be volume mapped for accurate dose control on FIB repair tools. The main issue complicating the use of SPM for metrology is the effect of tip shape and tip wear on the measurement data. For example, features with nearly vertical surfaces, like sidewalls, can't be measured accurately with conical tips because SPM scans will actually measure the sidewall of the tip and not the feature. This study will qualitatively address the issues associated with tip shape effects and discuss methods being employed to reduce or eliminate them.

This paper investigates possible solutions to intensity imbalance minimization for 65nm node application through rigorous vector simulations. It provides a strategic plan to select the right technology for AAPSM application. Technologies such as undercut, bias, combination of undercut and bias and use of a Transparent Etch Stop Layer (TESL) are compared. The study looks at the effect of through pitch, defocus, phase error and sidewall profile on space CD bias for the technologies mentioned to determine the set of conditions that would provide the best compromise between performance and manufacturability. Simulations indicate the use of TESL along with undercut would provide best compromise between manufacturability and performance. Simulation results show that performance can be improved considerably by optimizing phase target. The use of vertical side walls is sufficient if the purpose of simulation is to determine trends. For more accurate simulations it is suggested that the profile used in simulation be matched to profiles seen on manufactured AAPSM.