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Long write times have been an industry wide concern regarding rising mask costs. The purpose of this study is to develop a simple model that can predict mask write time precisely, without an e-beam writer. With a good understanding of the trade-offs between design complexity and write time, mask makers can work with mask designers more closely to simplify design and minimize mask cost. This work compared several basic models including calculations based on write area with a fixed e-beam shot size, a software estimation with a pre-set exposure, and a mask stage settling time. Our proposed model uses a completely different approach to examine the correlation between layout complexity (vertices count, total line edge, figure, etc.) through a CATS layout segmentation and actual write time. It is found that write time is a strong function of layout figure, vertex count and total line edge. Errors between actual write time and estimated write time from the new model reduced from 7% on average on the current production software to 3%. Additionally, the new model can operate independent of the writer type and without fractured data being transferred onto a writer. Also provided are a few case studies to evaluate the interaction between write time and basic shape/OPC (optical proximity correction). Using a simple design shape and a better data snapping strategy can reduce write time up to 10 fold for applications in nano-imprint template manufacturing. Several strategies to reduce mask cost are proposed.

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Wafer overlay is one of the key challenges for lithography in semiconductor device manufacturing, this becomes increasingly challenging following the shrinking of the device node. Some of Low k1 techniques, such as Double Exposure add additional burden to the overlay margin because on most critical layers the pattern is created based on exposures of 2 critical masks. Besides impact on overlay performance, any displacement between those two exposures leads to a significant impact on space CD uniformity performance as well. Mask registration is considered a major contributor to within-field wafer overlay.We investigated in-die registration performance on a critical poly-layer reticle in-depth, applying adaptive metrology rules, We used Thin-Plate-Splinefit (TPS) and Fourier analysis techniques for data analysis. Several systematic error components were observed, demonstrating the value of higher sampling to control mask registration performance

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