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20nm-node planar MONOS cell which has improved reliability is developed. Extremely wide program/erase Vth window and good retention characteristics after cycling stress are obtained by buried charge cell structure. Moreover, Vth shift by interference between adjacent cells has smaller dependence on the cell-cell space than Vth window improvement when the half pitch is constant. These results show that the buried charge planar MONOS cell is suitable for Flash memory with 20nm-node and beyond.

Reliable cost-effective ad small power amplifiers with high output power and efficiency are required for cellular handset phones. Present Si-MOS power-amplifier modules are inherently superior in terms of thermal stability and single-voltage operation, and yet their performance and size are comparable to or even better than those of GaAs-FET power-amplifier modules [l]. These modules are used by the majority of GSMcellular handset-phone manufacturers worldwide. since Li-ion batteries with high-energy densities have been widely used in cellular handset phones, 3.6V supply operation (3.6V system) is required for next-generation amplifier modules. However, a 3.6V 4W RF power-amplifier module has not yet been developed, even by using GaAs devices [2, 31.This Si power-MOS-amplifier module with 4W output power for a 3.6V system with 47% efficiency is assembled in a 0.2cc package that is as small as that of a monolithic IC with R F impedance-matched circuits. This work is the extension of Si-MOS RF modules, designed for a 4.8-V supply operation (4.8V system), that exhibit 4W output power and 45% efficiency 141. Although a 2A power MOSFET is sufficient in the previous 4.8V system, to realize a module with 4W output power and 50% efficiency at 9OOMHz operating frequency, a 3A power MOSFET is required in the 3.6V system. A 0.4pm gate Si power MOSFET technology meets the 3A requirement, and a low-loss RF impedance-matched circuit technique with divided device and collectively impedance matched amplification provides 4W output power. The trade-off between the circuit performance and the package area by is addressed usng an LC resonance circuit to maximize performance and minimize area.The 0 . 4~m gate Si high-frequency power MOSFET technology achieves 3A capability (at 9OOMHz operation) and low on-state resistance (smaller than 0.2pd36mm gate width, Wg) characteristics with breakdown voltage >lOV [51. However, the output power as high as 4W in the 3.6V system is difficult to achieve, because output power is not proportional t o device size (Wg) when Wg is larger than 40mm, and saturates at below 4W even if Wg is larger than 70mm, in the 900MHz-band (Figurel). This is due to the influence of a parasitic impedance associated with the source electrode. Furthermore, impedance-mismatch losses due to the decrease of input and output impedance also limits the output power. A divided-device and collectively impedancematched amplifier (DD-CIMA) technique overcomes these problems [61. This is a power MOSFET (with 36" Wg) pair combined in parallel and an amplifier constructed with collectively impedance-matched circuits (Figure 2). This technique attains output power >4W with 47% power-added efficiency in the 3.6V system. However, this approach increases package area, because it requires two input/output matched circuits. To addrewss this problem, an output impedance-matching configuration is used, in which an additional capacitor is inserted in each micro-stripline with optimized value and placement. As shown in Figure 3 length of the...