A sub-0.1 μm circuit design with substrate-over-biasing [CMOS logic]

Oowaki, Y.; Noguchi, M.; Takagi, Shinichi; Takashima, D.; Ono, Mizuki; Matsunaga, Y.; Sunouchi, K.; Kawaguchiya, H.; Matsuda, Shôichi; Kamoshida, Mototaka; Fuse, T.; Watanabe, Soichi; Toriumi, Akira; Manabe, Shiro; Hojo, Akimichi

doi:10.1109/isscc.1998.672387

Cited by 19 publications

(23 citation statements)

References 6 publications

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“…This scheme has been used in a 2-D discrete cosine transform core processor [60]. Furthermore, in the active mode, a slightly forward substrate bias can be used to increase the circuit speed while reducing SCEs [61]. Providing the body potential requires routing the body grid that adds to the overall chip area.…”

Section: B) Dual Threshold Cmosmentioning

confidence: 99%

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

2003

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Section: B) Dual Threshold Cmosmentioning

confidence: 99%

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

2003

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“…Speed Variation: The amount of speed variation for a given variation in designparameters is increased by lowering VDD• Control of VBB and internal VDD [20,21] in accordance with the parameter variations reduces the speed variation. Controlling a forward VBB is more effective in reducing speed variations [22,23] than controlling a reverse VBB• This is because the VT-VBB characteristics is more sensitive to VBB [1]. Forward VBB in [23], for example, reduced the variation of logic circuits and improved operation speed by 10%.…”

Section: Peripheral Logic Circuitsmentioning

confidence: 99%

Low-Voltage Embedded-RAM Technology: Present and Future

Itoh

Mizuno

2002

IFIP Advances in Information and Communication Technology

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Abstract:First, key issues for low-voltage «IV) embedded RAMs are summarized in terms of stable operation, suppression of leakage (gate-tunneling/subthreshold) currents, and speed variation of memory cells and peripheral logic circuits. Next, DRAM and SRAM cells to cope with the above issues, the circuit design focusing on subthreshold-current issue, and suppression of or compensation for design-parameter variations to reduce the speed variations are discussed. Voltage converters and power management for low-power and low-voltage operation are also explained. Finally, based on the above discussions, a perspective is given with emphasis on needs for simple/high signal-to-noise ratio memory cells (such as gain cells) with a pure logic compatible process, high-speed subthreshold-current reduction focusing on active mode, and memory-rich SoC architectures.

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“…At the circuit level, leakage reduction techniques include transistor stacking [3], reverse body biasing [4], dual threshold CMOS [5] and power gating [6]. Among these techniques, power gating is one of the most effective techniques for leakage reduction.…”

Section: Introductionmentioning

confidence: 99%

Implementation of power gating circuit for standby leakage power reduction

Subhashini

Geetha

2014

2014 International Conference on Electronics and Communication Systems (ICECS)

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This paper presents a technique which is called Asynchronous Adiabatic Power gated Logic (AAPL) which combines the benefit of both asynchronous and adiabatic logic. Each pipeline stage in the AAPL consists of adiabatic logic gate and handshake controller. Adiabatic logic gate is used to perform the logic function of the stage and the handshake controller is used to communicate with the neighboring devices and provide power to logic gates. In the AAPL circuit, logic gates obtain power and turn into active only when performing useful computations, and idle logic gates are not powered and thus have negligible leakage power dissipation. The Partial Charge Reuse (PCR) mechanism can also be integrated in this paper which is used to control the charge reuse between two stages.

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A sub-0.1 μm circuit design with substrate-over-biasing [CMOS logic]

Cited by 19 publications

References 6 publications

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Low-Voltage Embedded-RAM Technology: Present and Future

Implementation of power gating circuit for standby leakage power reduction

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