No abstract

Table 1 Comparison of potential sub-10 nm III-V device architectures Fig. 1 and 2 Schematic of ET-QW InAs MOSFETs and TEM images for L g = 50 nm ET-QW InAs MOSFETs with T QW = 5 nm. Note that 3-nm Al 2 O 3 was used as a gate insulator, together with MBE-grown 2-nm InP, leading to EOT = 2 nm. This paper reports Extremely-Thin-Body (ETB) InAs quantum-well (QW) MOSFETs with improved electrostatics down to L g = 50 nm (S =103 mV/dec, DIBL = 73 mV/V). These excellent metrics are achieved by using extremely thin body (1/3/1 nm InGaAs/InAs/InGaAs) quantum well structure with optimized layer design and a high mobility InAs channel.The ETB channel does not significantly degrade transport properties as evidenced by g m >1.5 mS/μm and v inj = 2.4 10 7 cm/s. Abstract:Introduction: The superior electron transport properties of III-V materials enable an attractive route to V dd scaling at sub 10 nm nodes. Extremely thin (ET) architectures (finFET or planar ETB) are a choice of technology at these geometries to maintain electrostatic integrity and control short channel effects (SCE) [1-3]. However, thinning down a channel degrades carrier transport properties. For the first time, we report ETB-QW L g = 50 nm InAs MOSFETs that exhibits excellent SCE control and favorably benchmarks an injection velocity (v inj ) against other III-V and Si devices. This comparison demonstrates that channel thickness can be scaled to at least 5 nm and the v inj advantage over Si maintained, demonstrating a potential scaling pathway to sub 10-nm technology node.Experimental: Table 1 as a motivation of this work compares different device architectures that can be considered for aggressively scaled III-V devices for future logic applications. The electrostatic control provided by ET-QW single gate devices may not be sufficient for sub-10nm nodes, but this architecture provides an excellent test structure to investigate the potential electron transport of multi-gate device with similar body/fin/nanowire width. Figs. 1 sand 2 show a cross-section of the device structure and corresponding TEM images of an L g = 50 nm device. MBE-grown 2-nm InP insulator was used to reduce access resistance and improve charge control, EOT and immunity to short channel effects as well as to improve D it [3].Extremely-Thin-Body of In 0.53 Ga 0.47 As/InAs/In 0.53 Ga 0.47 As (1/3/1nm) composite channel with inverted Si δ-doping and 5 nm In 0.52 Al 0.48 As spacer was chosen to improve carrier transport, electron confinement in the channel and electrostatic integrity. In a calibration structure, the Hall mobility was 8,400 cm 2 /V-s with n s,ch = 9.4 x 10 11 /cm 2 at 300 K. This is only about 24 % lower than the value obtained in a 10 nm thick In 0.7 Ga 0.3 As HEMT heterostructure [4], revealing that the use of 3-nm thin InAs sub-channel was effective in mitigating a degradation of carrier transport property.In 1D self-consistent Schrodinger-Poisson calculation for T QW = 5 nm epi structure, as the channel is thinned down, the carrier concentration in the channel at the acces...

This paper reports tri-gate sub-100 nm In 0.53 Ga 0.47 As QW MOSFETs with electrostatic immunity of S = 77 mV/dec., DIBL = 10 mV/V, together with excellent carrier transport of g m,max > 1.5 mS/µm, at V DS = 0.5 V. This result is the best balance of g m,max and S in any reported III-V MOSFETs. In addition, extracted compact model parameter including (μ 0 = 760 cm 2 /V-s and peak v x0 = 1.6×10 7 cm/s) indicate that InGaAs Tri-Gate MOSFETs would be a viable pathway to sub-10nm technology node.Introduction: Indium-rich InGaAs channel materials are a candidate for future low-power logic applications [1-2]. Tri-gate transistor architecture has been successfully demonstrated for improved electrostatics in Si MOSFETs [3][4] and most recently in III-V MOSFETs [5][6]. However, most of III-V tri-gate devices reported so far have shown wide fin geometry or poor interface quality between high-k dielectric and sidewall of etched Fin, failing to demonstrate performance and electrostatics benefit over the best ultrathin-body (UTB) planar III-V QW MOSFETs [7][8]. In this work, tri-gate In 0.53 Ga 0.47 As QW MOSFETs with bi-layer high-k dielectrics of Al 2 O 3 /HfO 2 are reported. In particular, L g = 60 nm tri-gate In 0.53 Ga 0.47 As QW MOSFETs with narrow fin width (W fin ) of 30 nm, fin height (H fin ) of 20 nm and EOT < 1 nm, yield excellent electrostatic integrity and performance benefit over UTB planar III-V MOSFETs, such as S = 77 mV/dec., DIBL = 10 mV/V, g m > 1.5 mS/µm and v ox = 1.6ⅹ10 7 cm/s. This result is significant because it shows that excellent electrostatics and performance can be achieved with high-k oxides directly on an etched tri-gate MOSFETs down to L g = 60 nm.

No abstract

ChemInform is a weekly Abstracting Service, delivering concise information at a glance that was extracted from about 100 leading journals. To access a ChemInform Abstract of an article which was published elsewhere, please select a “Full Text” option. The original article is trackable via the “References” option.