No abstract

200-mm and 300-mm device wafers were successfully thinned down to less than 10-µm. A 200-nm non-crystalline layer remaining after the high-rate Back Grind process was partially removed down to 50-nm by Ultra Poligrind process, or was completely removed with either Chemical Mechanical Planarization or Dry Polish. For FRAM device wafers thinned down to 9-µm, switching charge showed no change by the thinning process. CMOS logic device wafers thinned to 7-µm indicated neither change in I on current nor junction leakage current. Thinning such wafers to <10-µm will allow for lower aspect ratio less than 4 of Through-Silicon-Via (TSV) in a via-last process.

We investigated the dependence of temperature uniformity dufi ng millisecond annealing (MSA) on the pattern density and its effect on device characteristics and static random access memory (SRAM) yields with 45-nm node technology. By comparing flash lamp annealing (FLA) and laser spike annealing (LSA), we found FLA was diffi cult to use in our multiple MSA scheme without absorbing layers because of its high temperature uniformity sensitivity to pattern density. LSA was found to be more promising due to its lower sensitivity to pattern density and higher potential for enhancing performance. We also found hot spots were generated during LSA; however, these can easily be avoided by introducing LSA-friendly design rules.

No abstract