This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTLdesign and early floorplanning are performed. In this stage, logic contents are not known, but global structure of power/ground and clock networks, function partitioning and early floorplan give reasonable accuracy for global optimization of the chip. A case study shows the power voltage drop and critical path delay slowdown due to dynamic power voltage drop for a mixed analog-digital chip, and a good match with actual measurements is achieved.

No abstract

No abstract

This paper describes the design and observed performance of a 2‐modulus prescaler MSI developed for a pulse‐swallowing variable frequency divider at 1 GHz. The output of the final stage is fed directly back to the first stage to achieve high‐speed operation. The operating speed is 1 GHz for a source voltage of 5 ± 0.5 V and ambient temperature from −40 to +85 C; the maximum speed is 1.3 GHz. The power consumption is 400 ‐ 450 mW. The frequency division ratio is 1/64 and 1/65. Series gate ECLs are used for the basic circuit and the logic amplitude is 0.5 V. The chip size is 1.78 × 2.08 mm2 and includes 285 transistors and 170 resistors. Transistors with emitter size of 3 × 5 μm2 and quality n‐type resistors are used in the high‐speed circuit.