A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design

Abstract

This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTLdesign and early floorplanning are performed. In this stage, logic contents are not known, but global structure of power/ground and clock networks, function partitioning and early floorplan give reasonable accuracy for global optimization of the chip. A case study shows the power voltage drop and critical path delay slowdown due to dynamic power voltage drop for a mixed analog-digital chip, and a good match with actual measurements is achieved.

Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI

“…Insertion of on-chip decoupling capacitors near the switching devices on the substrate decreases the peak magnitude of the voltage drop. The total decoupling capacitor can be calculated by (4) and is reported in Table 1. It is assumed that the decoupling capacitors are uniformly distributed over the substrate surface.…”